HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 577

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

19.4.2
There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA
read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and
bus master I/O write. Of these, the chip's LPC supports only I/O read and I/O write cycles.
An LPC transfer cycle is started when the /)5$0( signal goes low in the bus idle state. If the
/)5$0( signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than B 0000 in the slave’s synchronization return cycle, but with the chip’s LPC a
value of B 0000 is always returned.
If the received address matches the host address in an LPC register (IDR, ODR, STR, TWR), the
host interface enters the busy state; it returns to the idle state by output of a state count 12
turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle
forced termination (abort) before state #12, registers and flags are not changed.
State
Count
1
2
3
4
5
6
7
8
9
10
11
12
13
Contents
Start
Cycle type/direction Host
Address 1
Address 2
Address 3
Address 4
Turnaround
(recovery)
Turnaround
Synchronization
Data 1
Data 2
Turnaround
(recovery)
Turnaround
LPC I/O Cycles
I/O Read Cycle
Host
Drive
Source
Host
Host
Host
Host
Host
None
Slave
Slave
Slave
Slave
None
Value
(3 to 0)
0000
0000
Bits 15 to
12
Bits 11 to 8
Bits 7 to 4
Bits 3 to 0
1111
ZZZZ
0000
Bits 3 to 0
Bits 7 to 4
1111
ZZZZ
Contents
Start
Cycle type/direction Host
Address 1
Address 2
Address 3
Address 4
Data 1
Data 2
Turnaround
(recovery)
Turnaround
Synchronization
Turnaround
(recovery)
Turnaround
Rev. 2.0, 08/02, page 537 of 788
I/O Write Cycle
Drive
Source
Host
Host
Host
Host
Host
Host
Host
None
Slave
Slave
None
Host
Value
(3 to 0)
0000
0010
Bits 15 to
12
Bits 11 to 8
Bits 7 to 4
Bits 3 to 0
Bits 3 to 0
Bits 7 to 4
1111
ZZZZ
0000
1111
ZZZZ