HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 304

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit
data written in TDR is transferred to TSR, and serial data transmission is started. Continuous
transmission is possible by writing the next transmit data to TDR during TSR serial data
transmission.
TDR can be read or written by the CPU at any time.
TDR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode.
Serial Mode Register (SMR)
SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for
the baud rate generator.
SMR can be read or written by the CPU at any time.
SMR is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode.
Bit 7—Communication Mode (COM): Bit 7 selects whether SCI3 operates in asynchronous
mode or synchronous mode.
Bit 7: COM
0
1
298
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
TDR7
COM
R/W
R/W
Description
Asynchronous mode
Synchronous mode
7
1
7
0
TDR6
CHR
R/W
R/W
6
1
6
0
TDR5
R/W
R/W
PE
5
1
5
0
TDR4
R/W
R/W
PM
4
1
4
0
STOP
TDR3
R/W
R/W
3
1
3
0
TDR2
R/W
R/W
MP
2
1
2
0
CKS1
TDR1
R/W
R/W
1
1
1
0
(initial value)
CKS0
TDR0
R/W
R/W
0
1
0
0