HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 312

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 4—Framing Error (FER): Bit 4 indicates that a framing error has occurred during reception
in asynchronous mode.
Bit 4: FER
0
1
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
Bit 3—Parity Error (PER): Bit 3 indicates that a parity error has occurred during reception with
parity added in asynchronous mode.
Bit 3: PER
0
1
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
306
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit
state.
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER
set to 1. In synchronous mode, neither transmission nor reception is possible when bit
FER is set to 1.
state.
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit PER is set to 1.
Description
Reception in progress or completed*
Clearing conditions:
After reading FER = 1, cleared by writing 0 to FER
A framing error has occurred during reception*
Setting conditions:
When the stop bit at the end of the receive data is checked for a value of 1 at
the end of reception, and the stop bit is 0*
Description
Reception in progress or completed*
Clearing conditions:
After reading PER = 1, cleared by writing 0 to PER
A parity error has occurred during reception*
Setting conditions:
When the number of 1 bits in the receive data plus parity bit does not match
the parity designated by bit PM in the serial mode register (SMR)
1
1
2
2
2
(initial value)
(initial value)