NAND04GA3C2A STMICROELECTRONICS [STMicroelectronics], NAND04GA3C2A Datasheet - Page 21

• Manufacturer Part Number: NAND04GA3C2A
• Description: 4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND04GA3C2A, NAND04GW3C2A
Figure 7.
6.5
RB
I/O
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the Cache Read operation has started, the Status Register can be read using the
Read Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the Cache Register
is ready to download new data.
To exit the Cache Read operation an Exit Cache Read command must be issued (see
Table
Cache Read Operation
Page Program
The Page Program operation is the standard operation to program data to the memory
array. Generally, data is programmed sequentially, however the device does support
Random Input within a page.
The memory array is programmed by page, however partial page programming is allowed
where any number of Bytes (1 to 2112) can be programmed.
Only one consecutive partial page program operations is allowed on the same page. After
exceeding this a Block Erase command must be issued before any further program
operations can take place in that page.
Setup
Read
Code
00h
8).
Address
Inputs
(Read Busy time)
tBLBH1
Confirm
Cache
Read
Code
31h
Busy
1st page
2nd page
Block N
3rd page
Data Output
last page
6 Device operations
Cache
Read
Code
Exit
34h
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