HYB18T512800B2F QIMONDA [Qimonda AG], HYB18T512800B2F Datasheet - Page 15

• Manufacturer Part Number: HYB18T512800B2F
• Description: 200-Pin SO-DIMM DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.3
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(
3.3.1
Speed Grade Definition:
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Rev. 1.1, 2007-01
08212006-PKYN-2H1B
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
Timing Characteristics
Speed Grade Definitions
Table 12
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
for DDR2–800;
V
REF
V
stabilizes. During the period before
TT
Symbol
t
t
t
t
t
t
t
t
.
CK
CK
CK
CK
RAS
RC
RCD
RP
Table 13
for DDR2–667 and
DDR2–800D
–2.5F
5–5–5
Min.
5
3.75
2.5
2.5
45
57.5
12.5
12.5
15
Speed Grade Definition Speed Bins for DDR2–800
8
Max.
8
8
8
70000
—
—
—
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
V
REF
Table 14
stabilizes, CKE = 0.2 x
Small Outlined DDR2 SDRAM Modules
DDR2–800E
–2.5
6–6–6
Min.
5
3.75
3
2.5
45
60
15
15
for DDR2–533C.
8
8
8
Max.
8
70000
—
—
—
t
CK
V
= 5ns with
DDQ
Internet Data Sheet
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
ns
CK
is recognized as low.
TABLE 12
t
RAS
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
= 40ns).
t
REFI
.