HYB18T512800B2F QIMONDA [Qimonda AG], HYB18T512800B2F Datasheet - Page 4

• Manufacturer Part Number: HYB18T512800B2F
• Description: 200-Pin SO-DIMM DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1.2
The Qimonda HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
module family are small outline DIMM modules “SO-DIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 32M × 64 (256 MB),
64M × 64 (512 MB) and 128M × 64 (1 GB) organization and
density, intended for mounting into 200-pin connector
sockets.
The memory array is designed with 512-Mbit Double-Data-
Rate-Two
Rev. 1.1, 2007-01
08212006-PKYN-2H1B
Product Type
PC2–6400
HYS64T32000EDL–25F–B2
HYS64T32900EDL–25F–B2
HYS64T64020EDL–25F–B2
HYS64T64920EDL–25F–B2
HYS64T128021EDL–25FB2
HYS64T128921EDL–25FB2
PC2–6400
HYS64T32000EDL–2.5–B2
HYS64T32900EDL–2.5–B2
HYS64T64020EDL–2.5–B2
HYS64T64920EDL–2.5–B2
HYS64T128021EDL–2.5B2
HYS64T128921EDL–2.5B2
PC2–5300
HYS64T32000EDL–3–B2
HYS64T32900EDL–3–B2
HYS64T64020EDL–3–B2
HYS64T64920EDL–3–B2
HYS64T128021EDL–3–B2
HYS64T128921EDL–3–B2
PC2–5300
HYS64T32000EDL–3S–B2
HYS64T32900EDL–3S–B2
HYS64T64020EDL–3S–B2
HYS64T64920EDL–3S–B2
HYS64T128021EDL–3S–B2
HYS64T128921EDL–3S–B2
(DDR2)
1)
Description
Synchronous
Compliance Code
256 MB 1R × 16 PC2–6400S–555–12–C0
512 MB 2R × 16 PC2–6400S–555–12–A0
1 GB 2R × 8 PC2-6400S–555–12–E0
256 MB 1R × 16 PC2–6400S–666–12–C0
512 MB 2R × 16 PC2–6400S–666–12–A0
1 GB 2R × 8 PC2-6400S–666–12–E0
256 MB 1R × 16 PC2–5300S–444–12–C0
512 MB 2R × 16 PC2–5300S–444–12–A0
1 GB 2R × 8 PC2-5300S–444–12–E0
256 MB 1R × 16 PC2–5300S–555–12–C0
512 MB 2R × 16 PC2–5300S–555–12–A0
1 GB 2R × 8 PC2-5300S–555–12–E0
DRAMs.
Decoupling
2)
4
Ordering Information for RoHS Compliant Products
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
device using the 2-pin I
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Description
1 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
1 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
1 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
1 Rank, Non-ECC
2 Rank, Non-ECC
2 Rank, Non-ECC
2
C protocol. The first 128 bytes are
Internet Data Sheet
SDRAM
Technology
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×16)
512 Mbit (×16)
512 Mbit (×8)
TABLE 2
2
PROM