HYB18T512800B2F QIMONDA [Qimonda AG], HYB18T512800B2F Datasheet - Page 29

• Manufacturer Part Number: HYB18T512800B2F
• Description: 200-Pin SO-DIMM DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1)
2)
3) Definitions for
4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode
5) For details and notes see the relevant Qimonda component data sheet
6)
Rev. 1.1, 2007-01
08212006-PKYN-2H1B
Parameter
Burst Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING.
All Bank Interleave Read Current
All banks are being interleaved at minimum
and address bus inputs are STABLE during DESELECTS.
Parameter
LOW
STABLE
FLOATING
SWITCHING
CK
CK
V
I
I
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
=
=
DD
DD1
DDQ
t
t
CK.MIN
CK.MIN.
specifications are tested after the device is properly initialized and
,
I
= 1.8 V ± 0.1 V;
DD4R
., Refresh command every
, Refresh command every
and
I
I
DD
Description
V
Inputs are stable at a HIGH or LOW level
Inputs are
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
DD7
IN
see
current measurements are defined with the outputs disabled (
≤
V
V
Table 3
DD
IL(ac).MAX
= 1.8 V ± 0.1 V
V
I
DD6
REF
, HIGH is defined as
current values are guaranteed up to
=
V
DDQ
t
t
RFC
RFC
/2
=
=
t
RC
t
t
REFI
RFC.MIN
without violating
interval, CKE is LOW and CS is HIGH between valid
V
interval, CKE is HIGH, CS is HIGH between valid
IN
≥
V
I
IH(ac).MIN
out
29
= 0 mA.
t
RRD
I
DD
T
parameter are specified with ODT disabled.
using a burst length of 4. Control
CASE
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
I
of 85 °C max.
OUT
= 0 mA). To achieve this on module level the output
Small Outlined DDR2 SDRAM Modules
I
DD2P
Definitions for
Internet Data Sheet
Symbol Note
I
I
I
I
DD5B
DD5D
DD6
DD7
TABLE 21
1)2)3)4)5)
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—
—
6)
I
DD