TMP47C990E TOSHIBA [Toshiba Semiconductor], TMP47C990E Datasheet
TMP47C990E
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TMP47C990E Summary of contents
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... ROM, RAM, input/output ports and timer/counters on a chip. The 47C101/201 are the standard type devices in the TLCS-47E series. RAM Package OTP DIP16 TMP47P201VP 64 x 4-bit SOP16 T.B.D. DIP16 TMP47P201VP 128 x 4-bit SOP16 T.B.D. TMP47C101/201 Piggyback + Adapter TMP47C990E + BM1160 (for DIP) 1/32 ...
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TMP47C101/201 Pin Assignment (Top View) Pin Function Pin Name Input/Output R43 to R40 I/O R53 to R50 R81 (T2) I/O (Input) R80 (INT2) XIN Input XOUT Output RESET Input HOLD (INT1) I/O (Input) VDD Power Supply VSS 2/32 4-bit I/O ...
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Operational Description Concerning the above component parts, the configuration and functions of hardwares are described. 1. System Configuration Internal CPU Function • 2.1 Program Counter (PC) • 2.2 Program Memory (ROM) • 2.3 H Register, L Register • 2.4 Data ...
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TMP47C101/201 2. Internal CPU Function 2.1 Program Counter (PC) The program counter is a 11-bit binary counter which indicates the address of the program memory storing the next instruc- tion to be executed.Normally, the PC is incremented by the The ...
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Program Memory (ROM) Programs and fixed data are stored in the program memory. The instruction to be executed next is read from the address indicated by the contents of the PC. The fixed data can be read by using ...
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TMP47C101/201 2.3 H Register and L Register The H register and L register are 4-bit general registers. They are also used as a register pair (HL) for the data memory (RAM) addressing pointer. The RAM consists of pages, each page ...
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Data Memory (RAM) The 47C101 has bits (addresses 00 the data memory (RAM), and the 47C201 has 128 x 4 bits (addresses 00 through The RAM is addressed in one of the ...
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TMP47C101/201 (1) Stack The stack provides the area in which the return address is saved before a jump is performed to the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When a ...
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Figure 2-8. Accessing Stack (Save/Restore) at the 47C201 (4) Count registers of the timer/counters (TC1, TC2) The 47C101/201 has two channels of 12-bit timer/ counters. The count register of the timer/counter is assigned with a RAM addresses in unit of ...
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TMP47C101/201 (5) Zero-page The 16 words (at addresses 00 zero page of the data memory can be used as the user flags or pointers by using zero-page addressing mode instructions (comparison, addition, transfer, and bit manipulation), providing enhanced efficiency in ...
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Zero detect information (Z) This information is “1” when the operation result or the data to be transferred to the accumulator/data mem- ory is “0000 ”. B Figure 2-11. ALU Example: The carry information and zero detect information for ...
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TMP47C101/201 (4) General flag (GF) This is a 1-bit general-purpose flag which can be set, cleared, or tested by program. 2.7. System Controller Figure 2-14. Clock Generator and Timing Generator 2.7.1 Clock Generator The clock generator provides the basic clock ...
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Timing Generator The timing generator produces the system clocks from basic clock pulse (CP) which are supplied to the SPU and the peripheral hardware. The timing generator provides the following functions: Generation of an internal source clock for interval ...
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TMP47C101/201 2.7.4 Hold Operating Mode The hold feature stops the system and holds the system’s internal states active before stop with a low power. The hold operation is controlled by the command register (OP10) and the HOLD pin input. The ...
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Edge-sensitive release (clock) mode In this mode, the hold operation is released at the ris- ing edge of the HOLD pin input. This mode is used for applications in which a relatively short-time program processing is repeated at a ...
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TMP47C101/201 The warm-up time is obtained by dividing the basic clock by the interval timer, so that, if the frequency at releasing the hold operation is unstable, the warm-up time shown in Figure 2-18. includes an error. There- fore, the ...
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Interrupt enable master flip-flop (EIF) The EIF controls the enable/disable of all interrupts. When this flip-flop is cleared to “0”, all interrupts are disabled; when it is set to “1”, the interrupts are enabled. When an interrupt is accepted, ...
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TMP47C101/201 Example 1: To enable IOVF1, INT1, and INT2 interrupts. LD A,#0101B XCH A,EIR EICLR IL,111111B Example 2: To set the EIF to “1”, and to clear the inter- rupt latches except ITMR to “0”. EICLR IL,000010B 2.8.2 Interrupt Processing ...
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In the interrupt processing, the program counter and flags are automatically saved or restored but the accumulator and other registers are not necessary to save or restore them, it must be performed by program as shown in ...
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TMP47C101/201 3. Peripheral Hardware Function 3.1 Ports The data transfer with the external circuit and the command/ status/data transfer with the internal circuit are performed by using the I/O instructions (13 kinds). There are 4 types of ports: I/O port ...
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Table 3-1. Port Address Assignments and Available I/O Instructions TOSHIBA CORPORATION TMP47C101/201 21/32 ...
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TMP47C101/201 (1) Ports R4 (R43 to R40), R5 (R53 to 50) These ports are 4-bit I/O ports with a latch. When used as an input port, the latch must be set to “1”. The latch is initialized to “1” during ...
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Interval Timer The interval timer can be used to generate an interrupt with a fixed frequency. For an interval timer interrupt (ITMR), one of 4 frequencies can be selected by command. The command reg- ister (OP19) is initialized to ...
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TMP47C101/201 3.3 Timer/Counters (TC1,TC2) The 47C101/201 contain two 12-bit timer/counters (TC1, TC2). RAM addresses are assigned to the count register in unit of 4 bits, permitting the initial value setting and counter reading Figure 3-16. Count Registers of the Timer/Counters ...
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The timer/counter increments at the rising edge of each count pulse. Counting starts with the first rising edge of the count pulse generated after the command has been set. Count operation is performed in one instruction cycle after the current ...
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TMP47C101/201 Example: To generate an overflow interrupt ( 4MHz) by the TC1 after 100ms. LD HL, #0F4H ST #9, @HL+ ST #7, @HL+ ST #0EH, @HL #1000B OUT A, %OP1C LD A, #0100B A EIR EICLR ...
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Input/Output Circuitry (1) Control pins (2) I/O Ports TOSHIBA CORPORATION The input/output circuitries of the 47C101/201 control pins are shown below, any one of the circuitries can be chosen by a code (FA mask ...
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TMP47C101/201 Electrical Characteristics Absolute Maximum Ratings (V SS Parameter Supply Voltage Input Voltage Output Voltage Output Current (Per 1 pin) Output Current (Total) Power Dissipation [ opr Soldering Temperature (time) Storage Temperature Operating Temperature Recommended Operating Conditions ...
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DC Characteristics ( opr Parameter Symbol Hysteresis Voltage IN1 Input Current I IN2 Input Resistance R IN Input Low Current I IL Output Leakage Current I LO Output High Voltage ...
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TMP47C101/201 Recommended Oscillating Conditions (V (1) 6MHz Ceramic Resonator CSA6.00MGU (MURATA) KBR-6.00MS (KYOCERA) EFOEC6004A4 (NATIONAL) (2) 4MHz Ceramic Resonator CSA4.00MG (MURATA) KBR-4.00MS (KYOCERA) EFOEC4004A4 (NATIONAL) Crystal Oscillator 204B-6F 4.0000 (TOYOCOM) C (3) 400kHz Ceramic Resonator CSB400B (MURATA) KBR-400B (KYOCERA) EFOA400K04B ...
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Typical Characteristics TOSHIBA CORPORATION TMP47C101/201 31/32 ...
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TMP47C101/201 32/32 Notes TOSHIBA CORPORATION ...