TMP47C990E TOSHIBA [Toshiba Semiconductor], TMP47C990E Datasheet - Page 18

• Manufacturer Part Number: TMP47C990E
• Description: CMOS 4-bit Microcontroller
• Manufacturer: TOSHIBA [Toshiba Semiconductor]

TMP47C101/201
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2.8.2 Interrupt Processing
An interrupt request is held until the interrupt is accepted or the
IL is cleared by the reset of the interrupt latch operation
instruction.The interrupt acknowledge processing is performed
in 2 instruction cycles after the end of the current instruction
execution (or after the timer/counter processing if any). The
interrupt service program terminates upon execution of the
interrupt return instruction [RETI].
interrupt service program, and the acceptable interrupt
source is selected by the EIR. However, for the INT1 interrupt,
the interrupt service is disabled under software control be-
cause it is not disabled by the EIR.
To perform the multi-interrupt, the EIF is set to “1” in the
Example: The INT1 interrupt service is disabled under
Example 1: To enable IOVF1, INT1, and INT2 interrupts.
Example 2: To set the EIF to “1”, and to clear the inter-
LD
XCH
EICLR IL,111111B
EICLR IL,000010B
software control (Bit 0 of RAM [05
signed to the disabling switch of interrupt ser-
vice).
rupt latches except ITMR to “0”.
A,#0101B
A,EIR
Figure 2-22. Interrupt Timing Chart (Example)
; EIR 0101
; EIF 1
; EIF 1, IL
IL
5
0
H
0
B
] are as-
0, IL
2
-
lowing sequence:
ing operations:
The interrupt acknowledge processing consists of the fol-
The Interrupt return instruction [RETI] performs the follow-
Restores the contents of the program counter and the
flags from the stack.
Sets the EIF to “1” to provide the interrupt enable state
again.
The contents of the program counter and the flags are
saved on the stack.
The interrupt entry address corresponding to the inter-
rupt source is set to the program counter.
The status flag is set to “1”.
The EIF is cleared to “0”, temporarily disabling the ac-
ceptance of subsequent interrupts.
The interrupt latch for the accepted interrupt source is
cleared to “0”.
The instruction stored at the interrupt entry address is
executed. (Generally, in the program memory space at
the interrupt entry address, the branch instruction to
each interrupt processing program is stored.)
PINT1:
SINT1:
TEST
B
RET1
:
05H,0 ; Skips if RAM [05
SINT1
TOSHIBA CORPORATION
is “1”
H
] 0