TMP47C990E TOSHIBA [Toshiba Semiconductor], TMP47C990E Datasheet - Page 14

• Manufacturer Part Number: TMP47C990E
• Description: CMOS 4-bit Microcontroller
• Manufacturer: TOSHIBA [Toshiba Semiconductor]

TMP47C101/201
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2.7.4 Hold Operating Mode
The hold feature stops the system and holds the system’s
internal states active before stop with a low power. The hold
operation is controlled by the command register (OP10) and
the HOLD pin input. The HOLD pin input state can be known
by the status register (IPOE). The HOLD pin is wired with the
R82 output latch. To use this port for hold operating mode, the
R82 output latch should be set to “1”.
(1)
Starts Hold Operating Mode
The hold operating mode consists of the level-sensitive
release mode and the edge-sensitive release mode.
The hold operation is started when the command is
set to the command register and holds the following
a. Level-sensitive release (back-up) mode
In this mode, the hold operation is released by setting
the HOLD pin to the high level. This mode is used for
the capacitor backup with power off or for the battery
backup for long hours.
If the instruction to start the hold operation is executed
with the HOLD pin input being high, the hold operation
does not start but the release sequence (warm-up)
starts immediately. Therefore, to start the hold opera-
tion in the level-sensitive release mode, that the HOLD
pin input being low (the hold operation request) must
be recognized in program. This recognition is per-
formed in one of the two ways below:
Figure 2-18. Hold Operating Mode Command Register/Status Register
states during the hold operation:
Example: To test HOLD to start the hold operation in
SHOLDH:
Testing HOLD (bit 0 of the status register)
Generating the external interrupt 1 request.
The oscillator stops and the system’s internal opera-
tions are all held up.
The timing generator is cleared to “0”.
The states of the data memory, registers, and latches
valid immediately before the system is put in the hold
state are all held.
The program counter holds the address of the in-
struction to be executed after the instruction ([OUT A,
%OP10] or [OUT @HL, %OP10]) which starts the
hold operating mode.
the level-sensitive release mode (the warm-
up time = 2
TEST
B
LD
OUT
14
%IPOE, 0
SHOLDH
A, #1101B ; OP10 1101
A, %OP10
/fc).
TOSHIBA CORPORATION
; Waits until
HOLD pin input
goes low.
B