ATXMEGA128B3-AU ATMEL [ATMEL Corporation], ATXMEGA128B3-AU Datasheet - Page 75
ATXMEGA128B3-AU
Manufacturer Part Number
ATXMEGA128B3-AU
Description
8/16-bit Atmel XMEGA B3 Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATXMEGA128B3-AU.pdf
(137 pages)
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Table 36-10. Clock and timing.
Table 36-11. Accuracy characteristics.
8074B–AVR–02/12
Symbol
Symbol
Clk
DNL
f
INL
ClkADC
RES
f
ADC
ADC
(1)
(1)
Parameter
ADC Clock frequency
Sample rate
Sample rate
Sampling Time
Conversion time (latency)
Start-up time
ADC settling time
Parameter
Resolution
Integral non-linearity
Differential non-linearity
Offset Error
12-bit resolution
Differential mode
Single ended
unsigned mode
Differential mode
Single ended
unsigned mode
Differential mode
Maximum is 1/4 of Peripheral clock
frequency
Measuring internal signals
Current limitation (CURRLIMIT) off
CURRLIMIT = LOW
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
1/2 Clk
(RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12
ADC clock cycles
After changing reference or input mode
ADC
cycle
Condition
Differential
Single ended signed
Single ended unsigned
16ksps, V
16ksps, all V
300ksps, V
300ksps, all V
16ksps, V
16ksps, all V
16ksps, V
16ksps, all V
300ksps, V
300ksps, all V
16ksps, V
16ksps, all V
300ksps, V
Temperature drift, V
Operating voltage drift
Condition
(2)
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
= 3V
= 3.0V
= 3V
= 3.0V
REF
REF
=3V
= 3V
= 3V
REF
=3V
Min.
0.25
100
Min.
16
16
6
8
7
8
Typ.
125
Typ.
0.35
0.01
0.16
12
0.5
0.8
0.6
0.5
1.3
0.3
0.5
0.5
0.6
0.6
12
11
12
7
-7
1
XMEGA B3
Max.
1800
Max.
300
300
250
150
50
10
24
5
7
12
11
12
1
2
1
2
1
2
1
1
1
1
1
1
Clk
Clk
cycles
cycles
Units
ksps
ksps
Units
mV/K
mV/V
kHz
Bits
µs
mV
lsb
ADC
ADC
75
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