AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 194

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

14.5.3.2
32099D–06/2010
Closed Loop Operation
COARSE and FINE fields, and thereby the output frequency of the DFLL, while the DFLL is
enabled and in use.
The DFLL clock is ready to be used when PCLKSR.DFLL0RDY is cleared after enabling the
DFLL.
To select closed loop operation, the user must write a one to the DFLL0CONF.MODE bit and the
DFLL0CONF.EN bits. The output frequency of the DFLL is given by:
The COARSE and FINE fields in DFLL0CONF register are read-only in closed loop mode, and
are controlled by the DFLLIF to meet user specified frequency. The values in the COARSE reg-
ister when the closed loop mode is enabled is used by the frequency tuner as a starting point for
the COARSE value. Setting the COARSE to a value believed to be the correct will reduce the
time needed to get a lock on the coarse value. To set up the DFLLIF first enable the DFLL by
writing one to EN bit in DFLL0CONF register. Then enable and select a reference clock
(CLK_DFLLIF_REF). CLK_DFLLIF_REF is a generic clock, please refer to Generic Clocks
chapter for details. Then set the maximum step size allowed in finding the COARSE and FINE
values by setting the CSTEP and FSTEP bits in DFLL0STEP register. A small step size will
ensure low overshoot on the output frequency, but will typically be slower. A high value might
give a big overshoot, but will typically give faster locking. DFLL0STEP.CSTEP and
D F L L 0 S T E P . F S T E P s h o u l d b e s e t l o w e r t h a n 5 0 % o f t h e m a x i m u m v a l u e o f
DFLL0CONF.COARSE and DFLL0CONF.FINE respectively. Then set the value of IMUL and
FMUL fields in the DFLL0MUL register, care must be taken when choosing IMUL and FMUL so
the output frequency does not exceed the maximum frequency of the device.
The locking of the frequency in closed loop mode is divided into three stages. In the COARSE
stage the control logic quickly finds the correct value for the COARSE field in DFLL0CONF reg-
ister and thereby setting the output frequency to a value close to the correct frequency. The
DFLL0LOCKC interrupt is issued when this is done. In the FINE stage the control logic tunes the
value in the FINE field in the DFLL0CONF register so the output frequency very close to the
desired frequency. The DFLL0LOCKF interrupt is issued when this is done. In the ACCURATE
stage the DFLL frequency tuning mechanism uses dithering on the FINE bits to obtain an accu-
rate output frequency. When the accurate frequency is obtained the DFLL0LOCKA interrupt is
issued. The ACCURATE stage will only be executed if DITHER bit in DFLL0CONF register has
been written to one. If DITHER is written to zero DFLL0LOCKA will never occur. If dithering is
enabled, the frequency of the dithering is decided by a generic clock (CLK_DFLLIF_DITHER).
This clock has to be set up correctly before enabling dithering. Please refer to the Generic
Clocks chapter for details. The flow for finding the correct settings is shown in
page
When dithering is enable the accuracy of the average output frequency of the DFLL will be
higher. However, the frequency will be alternating between two frequencies. If a fixed frequency
is required, the dithering should not be enabled.
The DFLL clock is ready to be used when PCLKSR.DFLL0RDY is cleared after enabling the
DFLL. However, the accuracy of the outputed frequency depends on which locks that are set.
The frequency tuner will automatically compensate for drift in the output frequency of the VCO
without losing either of the locks. If the FINE register overflows or underflows, which should nor-
195.
f
vco
=


IMUL
+
FMUL
---------------- -
2
16
 f

AT32UC3L016/32/64
ref
Figure 14-3 on
194