AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 511

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

23.8.2.2
23.8.2.3
32099D–06/2010
Setting Up and Performing a Transfer
Address Matching
Figure 23-6. Bus Timing Diagram
Operation of TWIS is mainly controlled by the Control Register (CR). The following list pres-
ents the main steps in a typical communication:
The interrupt system can be set up to give interrupt request on specific events or error condi-
tions, for example when a byte has been received.
The NBYTES register is only used in SMBus mode, when PEC is enabled. In I²C mode or in
SMBus mode when PEC is disabled, the NBYTES register is not used, and should be written
to 0. NBYTES is updated by hardware, so in order to avoid hazards, software updates of
NBYTES can only be done through writes to the NBYTES register.
TWIS can be set up to match several different addresses. More than one address match may
be enabled simultaneously, allowing TWIS to be assigned to several addresses. The address
matching phase is initiated after a START or REPEATED START condition. When TWIS
receives an address that generates an address match, an ACK is automatically returned to the
master.
In I²C mode:
In SMBus mode:
1. Before any transfers can be performed, bus timings must be configured by program-
2. If a DMA controller is to be used for the transfers, it must be set up.
3. The Control Register (CR) must be configured with information such as the slave
• The address in CR.ADR is checked for address match if CR.SMATCH is set.
• The General Call address is checked for address match if CR.GCMATCH is set.
S
ming the Timing Register (TR).
address, SMBus mode, Packet Error Checking (PEC), number of bytes to transfer,
and which addresses to match.
t
t LOW
HD:STA
t
SU:DAT
t HIGH
t
HD:DAT
t LOW
t
t
SU:DAT
SU:STA
AT32UC3L016/32/64
Sr
t
SU:STO
P
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