AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 383

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

32099D–06/2010
In SPI Master Mode:
In SPI Slave Mode:
• the external clock CLK must not be selected (USCLKS … 0x3), and the bit CLKO must be set
• to obtain correct behavior of the receiver and the transmitter, the value programmed in CD of
• if the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must
• the external clock (CLK) selection is forced regardless of the value of the USCLKS field in the
• to obtain correct behavior of the receiver and the transmitter, the external clock (CLK)
to “1” in the Mode Register (MR), in order to generate correctly the serial clock on the CLK
pin.
must be superior or equal to 4.
be even to ensure a 50:50 mark/space ratio on the CLK pin, this value can be odd if the
internal clock is selected (CLK_USART).
Mode Register (MR). Likewise, the value written in BRGR has no effect, because the clock is
provided directly by the signal on the USART CLK pin.
frequency must be at least 4 times lower than the system clock.
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