P89LPC915FDH NXP [NXP Semiconductors], P89LPC915FDH Datasheet - Page 48

• Manufacturer Part Number: P89LPC915FDH
• Description: 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter
• Manufacturer: NXP [NXP Semiconductors]

Philips Semiconductors
9397 750 14397
Product data
Fig 16. SPI block diagram (P89LPC916).
SPI STATUS REGISTER
BY 4, 16, 64, 128
CPU clock
DIVIDER
SELECT
SPI CONTROL
The SPI interface has four pins: SPICLK, MOSI, MISO, and SS:
Typical connections are shown in
•
•
interrupt
request
SPI clock (master)
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and
flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal
is output in the master mode and is input in the slave mode. If the SPI system is
disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port
functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave
device uses its SS pin to determine whether it is selected.
SPI
MSTR
SPEN
Rev. 04 — 17 December 2004
internal
data
bus
8-bit microcontrollers with accelerated two-clock 80C51 core
SPI CONTROL REGISTER
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK LOGIC
Figure
clock
17, 18, and 19.
P89LPC915/916/917
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
M
M
M
S
S
S
002aaa497
SPICLK
MISO
MOSI
P2.3
P2.2
P2.5
P2.4
SS
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