LPC1111 NXP [NXP Semiconductors], LPC1111 Datasheet - Page 27

• Manufacturer Part Number: LPC1111
• Description: 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash and 8 kB SRAM
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC1111_12_13_14_1
Product data sheet
CAUTION
7.16.2 Brownout detection
7.16.3 Code security (Code Read Protection - CRP)
7.16.4 APB interface
7.16.5 AHBLite
The LPC1111/12/13/14 includes four levels for monitoring the voltage on the V
this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal
to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
This feature of the LPC1111/12/13/14 allows user to enable different levels of security in
the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC111x user manual.
There are three levels of Code Read Protection:
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC111x user manual.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
1. CRP1 disables access to the chip via the SWD and allows partial flash update
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
3. Running an application with level CRP3 selected fully disables any access to the chip
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
update using a reduced set of the ISP commands.
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the UART.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 16 April 2010
32-bit ARM Cortex-M0 microcontroller
LPC1111/12/13/14
© NXP B.V. 2010. All rights reserved.
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pin. If
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