LPC2888FET180/01 NXP [NXP Semiconductors], LPC2888FET180/01 Datasheet - Page 17

• Manufacturer Part Number: LPC2888FET180/01
• Description: 16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2880_LPC2888_3
Preliminary data sheet
6.7.1 Features
6.8.1 Features
6.7 GPIO
6.8 Interrupt controller
Remark: Synchronous static memory devices (synchronous burst mode) are not
supported.
Many device pins that are not needed for a specific peripheral function can be used as
GPIOs. These pins can be controlled by the mode registers. Pins may be dynamically
configured as inputs or outputs. Separate registers allow setting or clearing any number of
outputs simultaneously. The current state of the port pins may be read back via the PIN
registers.
The interrupt controller accepts all of the interrupt request inputs and categorizes them as
FIQ or IRQ. The programmable assignment scheme means that priorities of interrupts
from the various peripherals can be dynamically assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the interrupt
controller combines the requests to produce the FIQ signal to the ARM processor.
The interrupt controller combines the requests from all the vectored IRQs to produce the
IRQ signal to the ARM processor. The IRQ service routine can start by reading a register
from the interrupt controller and jumping there.
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– 2 MB address range with three chip selects.
One chip select for synchronous memory and three chip selects for static memory
devices.
Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
Dynamic memory self-refresh mode controlled by software.
Controller supports 2048, 4096, and 8192 row address synchronous memory parts.
That is typically 512 MB, 256 MB, and 128 MB parts, with 4, 8, or 16 data lines per
device.
81 pins have dual use as a specific function I/O or as a GPIO.
Each dual use pin can be programmed for functional I/O, drive high, drive low, or
hi-Z/input.
Four pins are dedicated as GPIO, programmable for drive high, drive low, or
hi-Z/input.
Maps all LPC2880/2888 interrupt sources to processor FIQ and IRQ
Level sensitive sources
Programmable priority among sources
Nested interrupt capability
Software interrupt capability for each source
16/32-bit ARM microcontrollers with external memory interface
Rev. 03 — 17 April 2008
LPC2880; LPC2888
© NXP B.V. 2008. All rights reserved.
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