LPC2888FET180/01 NXP [NXP Semiconductors], LPC2888FET180/01 Datasheet - Page 32

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LPC2888FET180/01

Manufacturer Part Number
LPC2888FET180/01
Description
16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface
Manufacturer
NXP [NXP Semiconductors]
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2888FET180/01
Manufacturer:
HYNIX
Quantity:
1 200
NXP Semiconductors
Table 8.
C
[1]
[2]
[3]
[4]
[5]
[6]
LPC2880_LPC2888_3
Preliminary data sheet
Symbol
Common to read and write cycles
t
Read cycle parameters
t
t
t
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
t
t
t
t
CSLAV
OELAV
BLSLAV
CSLOEL
CSLBLSL
OELOEH
BLSLBLSH
su(DQ)
h(DQ)
CSHOEH
CSHBLSH
OEHANV
BLSHANV
CSLDV
CSLWEL
CSLBLSL
WELDV
WELWEH
BLSLBLSH
WEHANV
WEHDNV
BLSHANV
BLSHDNV
L
= 25 pF, T
Refer to the LPC2800 user manual UM10208_2 for the programming of WAITOEN and HCLK.
Refer to the LPC2800 user manual UM10208_2 for the programming of WAITRD and HCLK.
(WAITRD
Refer to the LPC2800 user manual UM10208_2 for the programming of WAITWEN and HCLK.
Refer to the LPC2800 user manual UM10208_2 for the programming of WAITWR and HCLK.
(WAITWD
Dynamic characteristics: static external memory interface
Parameter
CS LOW to address valid
time
OE LOW to address valid
time
BLS LOW to address valid
time
CS LOW to OE LOW time
CS LOW to BLS LOW time
OE LOW to OE HIGH time
BLS LOW to BLS HIGH time
data input/output set-up time
data input/output hold time
CS HIGH to OE HIGH time
CS HIGH to BLS HIGH time
OE HIGH to address invalid
time
BLS HIGH to address invalid
time
CS LOW to data valid time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
WE LOW to WE HIGH time
BLS LOW to BLS HIGH time
WE HIGH to address invalid
time
WE HIGH to data invalid time
BLS HIGH to address invalid
time
BLS HIGH to data invalid
time
amb
WAITOEN + 1) = 3 min at 60 MHz.
WAITWEN + 1) = 3 min at 60 MHz.
= 20 C, V
DD1(EMC)
= V
DD2(EMC)
Conditions
= 3.3 V and 1.8 V.
16/32-bit ARM microcontrollers with external memory interface
Rev. 03 — 17 April 2008
[1][2][3]
[1][2][3]
[4][5][6]
[4][5]
[1]
[1]
[1]
[4]
[4]
[4]
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
0
0
0
0 + WAITOEN
0 + WAITOEN
(WAITRD
(WAITRD
33.3
0
0
0
2
2
0
(WAITWEN + 1)
WAITWEN
0
(WAITWR
(WAITWR
1
1
0
0
WAITOEN
WAITOEN
HCLK
HCLK
(WAITWEN + 1)
HCLK
HCLK
LPC2880; LPC2888
WAITOEN + 1)
WAITOEN + 1)
WAITWEN + 1)
WAITWEN + 3)
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
© NXP B.V. 2008. All rights reserved.
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
32 of 43
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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