LPC2917/01 NXP [NXP Semiconductors], LPC2917/01 Datasheet - Page 17
LPC2917/01
Manufacturer Part Number
LPC2917/01
Description
ARM9 microcontroller with CAN and LIN
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.LPC291701.pdf
(86 pages)
- Current page: 17 of 86
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NXP Semiconductors
LPC2917_19_01_2
Preliminary data sheet
Fig 4.
AHB MULTILAYER MATRIX
AHB TO APB BRIDGES
FLASH/SRAM/SMC
peripheral subsystem
SYSTEM CONTROL
LPC2917/2919/01 block diagram, overview of clock areas
EVENT ROUTER
general subsytem
TIMER 0/1/2/3
GPIO0/1/2/3
UART0/1
SPI0/1/2
GPDMA
WDT
CFID
VIC
CPU
Two of the base clocks generated by the CGU0 are used as input into a second, dedicated
CGU (CGU1). The CGU1 uses its own PLL and fractional divider to generate the base
clock for an independent clock output.
BASE_SYS_CLK
CGU0
branch
clocks
Rev. 02 — 17 June 2009
BA SE_ICLK0_CLK
BASE_ICLK1_CLK
BASE_IVNSS_CLK
BASE_MSCSS_CLK
BASE_PCR_CLK
LPC2917/01; LPC2919/01
branch
branch
clocks
clock
branch
branch
clocks
clocks
ARM9 microcontroller with CAN and LIN
modulation and sampling
networking subsystem
power control subsystem
control subsystem
BASE_OUT_CLK
ACCEPTANCE
GENERATION AND
TIMER0/1 MTMR
RESET/CLOCK
MANAGEMENT
GLOBAL
PWM0/1/2/3
FILTER
LIN0/1
I2C0/1
CAN0/1
ADC1/2
CGU1
POWER
QEI
branch
clock
© NXP B.V. 2009. All rights reserved.
002aad962
CLOCK
OUT
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