STR910FAZ32H6T STMICROELECTRONICS [STMicroelectronics], STR910FAZ32H6T Datasheet - Page 17

• Manufacturer Part Number: STR910FAZ32H6T
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STR91xFAx32 STR91xFAx42 STR91xFAx44
3.8
3.8.1
Table 6.
3.9
3.9.1
Production salestype
STR91xFAxxxxx
STR91xFAxxxxx
STR91xFAxxxxx
STR91xFxxxxx
One-time-programmable (OTP) memory
There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory
calibration constants, or other permanent data constants. These OTP data bytes can be
programmed only one time through either the JTAG interface or by the CPU, and these
bytes can never be altered afterwards. As an option, a “lock bit” can be set by the JTAG
interface or the CPU which will block any further writing to the this OTP area. The “lock bit”
itself is also OTP. If the OTP array is unlocked, it is always possible to go back and write to
an OTP byte location that has not been previously written, but it is never possible to change
an OTP byte location if any one bit of that particular byte has been written before. The last
two OTP bytes (bytes 31 and 30) are reserved for the STR91xFA product ID and revision
level.
Product ID and revision level
OTP bytes 31 and 30 are programmed at ST factory before shipment and may be read by
firmware to determine the STR91xFA product type and silicon revision so it can optionally
take action based on the silicon on which it is running. In Rev H devices, byte 31 contains
the the major family identifier of "9" (for STR9) in the high-nibble location and the minor
family identifier in the low nibble location, which can be used to determine the size of
Primary flash memory. In all devices, byte 30 contains the silicon revision level indicator.
See
Primary Flash memory. See
revisions.
Product ID and revision level values
Vectored interrupt controller (VIC)
Interrupt management in the STR91xFA is implemented from daisy-chaining two standard
ARM VIC units. This combined VIC has 32 prioritized interrupt request channels and
generates two interrupt output signals to the CPU. The output signals are FIQ and IRQ, with
FIQ having higher priority.
FIQ handling
FIQ (Fast Interrupt reQuest) is the only non-vectored interrupt and the CPU can execute an
Interrupt Service Routine (ISR) directly without having to determine/prioritize the interrupt
source, minimizing ISR latency. Typically only one interrupt source is assigned to FIQ. An
FIQ interrupt has its own set of banked registers to minimize the time to make a context
switch. Any of the 32 interrupt request input signals coming into the VIC can be assigned to
FIQ.
Table 6
for values related to the revisions of STR9 production devices and size of
Silicon revision
Rev D
Rev G
Rev H
Rev H
Section 8
Size of Primary Flash
for details of external identification of silicon
256K or 512K
256K or 512K
256K
512K
OTP byte 31
91h
91h
90h
91h
Functional overview
OTP byte 30
03h
21h
21h
20h
17/99