STR910FAZ32H6T STMICROELECTRONICS [STMicroelectronics], STR910FAZ32H6T Datasheet - Page 27

• Manufacturer Part Number: STR910FAZ32H6T
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STR91xFAx32 STR91xFAx42 STR91xFAx44
3.15
pin. The current drawn by the RTC unit on the VBATT pin is very low in this standby mode,
I
JTAG interface
An IEEE-1149.1 JTAG interface on the STR91xFA provides In-System-Programming (ISP)
of all memory, boundary scan testing of pins, and the capability to debug the CPU.
STR91xFA devices are shipped from ST with blank Flash memories. The CPU can only boot
from Flash memory (selection of which Flash bank is programmable). Firmware must be
initially programmed through JTAG into one of these Flash memories before the STR91xFA
is used.
Six pins are used on this JTAG serial interface. The five signals JTDI, JTDO, JTMS, JTCK,
and JTRSTn are all standard JTAG signals complying with the IEEE-1149.1 specification.
The sixth signal, JRTCK (Return TCK), is an output from the STR91xFA and it is used to
pace the JTCK clock signal coming in from the external JTAG test equipment for debugging.
The frequency of the JTCK clock signal coming from the JTAG test equipment must be at
least 10 times less than the ARM966E-S CPU core operating frequency (f
ensure this, the signal JRTCK is output from the STR91xFA and is input to the external
JTAG test equipment to hold off transitions of JTCK until the CPU core is ready, meaning
that the JTAG equipment cannot send the next rising edge of JTCK until the equipment
receives a rising edge of JRTCK from the STR91xFA. The JTAG test equipment must be
able to interpret the signal JRTCK and perform this adaptive clocking function. If it is known
that the CPU clock will always be at least ten times faster than the incoming JTCK clock
signal, then the JRTCK signal is not needed.
The two die inside the STR91xFA (CPU die and Flash memory die) are internally daisy-
chained on the JTAG bus, see
Ports (TAPs), one for boundary scan functions and one for ARM CPU debug. The Flash
memory die has one TAP for program/erase of non-volatile memory. Because these three
TAPs are daisy-chained, only one TAP will converse on the JTAG bus at any given time while
the other two TAPs are in BYPASS mode. The TAP positioning order within this JTAG chain
is the boundary scan TAP first, followed by the ARM debug TAP, followed by the Flash TAP.
All three TAP controllers are reset simultaneously by one of two methods:
●
●
This means that chip-level system resets from watchdog time-out or the assertion of
RESET_INn pin do not affect the operation of any JTAG TAP controller. Only global resets
effect the TAPs.
RTC_STBY
A chip-level global reset, caused only by a Power-On-Reset (POR) or a Low Voltage
Detect (LVD).
A reset command issued by the external JTAG test equipment. This can be the
assertion of the JTAG JTRSTn input pin on the STR91xFA or a JTAG reset command
shifted into the STR91xFA serially.
.
Figure 3 on page
28. The CPU die has two JTAG Test Access
Functional overview
CPUCLK
). To
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