STR910FM32X6T STMICROELECTRONICS [STMicroelectronics], STR910FM32X6T Datasheet - Page 10

• Manufacturer Part Number: STR910FM32X6T
• Description: ARM966E-S 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC Motor Control, 4 Timers, ADC, RTC, DMA
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Functional overview
2.5
2.5.1
2.5.2
2.6
2.7
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SRAM (64K or 96K Bytes)
A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-cycle
data accesses. As shown in
High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the DMA
unit on the AHB to also access to the SRAM.
Arbitration
Zero-wait state access occurs for either the D-TCM or the AHB when only one of the two is
requesting SRAM. When both request SRAM simultaneously, access is granted on an
interleaved basis so neither requestor is starved, granting one 32-bit word transfer to each
requestor before relinquishing SRAM to the other. When neither the D-TCM or the AHB are
requesting SRAM, the arbiter leaves access granted to the most recent user (if D-TCM was last
to use SRAM then the D-TCM will not have to arbitrate to get access next time).
The CPU may execute code from SRAM through the AHB. There are no wait states as long as
the D-TCM is not contending for SRAM access. The ARM966E-S CPU core has a small pre-
fetch queue built into this instruction path through the AHB to look ahead and fetch instructions
during idle bus cycles.
Battery backup
When a battery is connected to the designated battery backup pin (VBATT), SRAM contents
are automatically preserved when the normal operating voltage on VDD pins is lost or sags
below threshold. Automatic switchover to SRAM can be disabled by firmware if it is desired that
the battery will power only the RTC and not the SRAM during standby.
DMA data movement
DMA channels on the Advanced High-performance Bus (AHB) take full advantage of the
separate data path provided by the Harvard architecture, moving data rapidly and largely
independent of the instruction path. There are two DMA units, one is dedicated to move data
between the Ethernet interface and SRAM, the other DMA unit has eight programmable
channels with 16 request signals to service other peripherals and interfaces (USB, SSP, I2C,
UART, Timers, EMI, and external request pins). Both single word and burst DMA transfers are
supported. Memory-to-memory transfers are supported in addition to memory-peripheral
transfers. DMA access to SRAM is shared with D-TCM accesses, and arbitration is described
in
tables.
Non-volatile memories
There are two independent 32-bit wide Burst Flash memories enabling true read-while-write
operation. The Flash memories are single-voltage erase/program with 20 year minimum data
retention and 100K minimum erase cycles. The primary Flash memory is much larger than the
secondary Flash.
Section
2.5.1. Efficient DMA transfers are managed by firmware using linked list descriptor
Figure
1, the D-TCM shares SRAM access with the Advanced
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