STR910FM32X6T STMICROELECTRONICS [STMicroelectronics], STR910FM32X6T Datasheet - Page 11

• Manufacturer Part Number: STR910FM32X6T
• Description: ARM966E-S 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC Motor Control, 4 Timers, ADC, RTC, DMA
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STR91xF
2.7.1
2.7.2
2.8
2.9
2.9.1
Primary Flash memory
Using the STR91xF device configuration software tool, it is possible to specify that the primary
Flash memory is the default memory from which the CPU boots at reset, or otherwise specify
that the secondary Flash memory is the default boot memory. This choice of boot memory is
non-volatile and stored in a location that can be programmed and changed only by JTAG In-
System Programming. See
The primary Flash memory has equal length 64K byte sectors. Devices with 256 Kbytes of
primary Flash have four sectors and 512K devices have eight sectors.
Secondary Flash memory
The smaller of the two Flash memories can be used to implement a bootloader, capable of
storing code to perform robust In-Application Programming (IAP) of the primary Flash memory.
The CPU executes code from the secondary Flash, while updating code in the primary Flash
memory. New code for the primary Flash memory can be downloaded over any of the
interfaces on the STR91xF (USB, Ethernet, CAN, UART, etc.)
Additionally, the Secondary Flash memory may also be used to store small data sets by
emulating EEPROM though firmware, eliminating the need for external EEPROM memories.
This raises the data security level because passcodes and other sensitive information can be
securely locked inside the STR91xF device.
The secondary Flash memory has four equal length sectors of 8 Kbytes each.
Both the primary Flash memory and the secondary Flash memory can be programmed with
code and/or data using the JTAG In-System Programming (ISP) channel, totally independent of
the CPU. This is excellent for iterative code development and for manufacturing.
One-time-programmable (OTP) memory
There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory
calibration constants, or other permanent data constants. These OTP data bytes can be
programmed only one time through either the JTAG interface or by the CPU, and these bytes
can never be altered afterwards. As an option, a “lock bit” can be set by the JTAG interface or
the CPU which will block any further writing to the this OTP area. The “lock bit” itself is also
OTP. If the OTP array is unlocked, it is always possible to go back and write to an OTP byte
location that has not been previously written, but it is never possible to change an OTP byte
location if any one bit of that particular byte has been written before. The last two OTP bytes are
reserved for the STR91xF product ID and revision level.
Vectored interrupt controller (VIC)
Interrupt management in the STR91xF is implemented from daisy-chaining two standard ARM
VIC units. This combined VIC has 32 prioritized interrupt request channels and generates two
interrupt output signals to the CPU. The output signals are FIQ and IRQ, with FIQ having higher
priority.
FIQ handling
FIQ (Fast Interrupt reQuest) is the only non-vectored interrupt and the CPU can execute an
Interrupt Service Routine (ISR) directly without having to determine/prioritize the interrupt
Section 5: Memory
mapping, for more detail.
Functional overview
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