LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 102
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 102 of 284
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March 22, 2006
Reset
Reset
Type
Type
GPIO Interrupt Sense (GPIOIS)
Offset 0x404
RO
RO
31
15
0
0
31:8
7:0
Bit
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
RO
RO
30
14
0
0
reserved
Name
IS
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0x00
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPIO Interrupt Sense
0: Edge on corresponding pin is detected (edge-sensitive)
1: Level on corresponding pin is detected (level-sensitive)
RO
RO
24
0
8
0
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
IS
R/W
RO
19
0
3
0
LM3S101 Data Sheet
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
102
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