LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 78
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 78 of 284
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March 22, 2006
Reset
Reset
Type
Type
Bit/Field
Clock Verification Clear (CLKVCLR)
Offset 0x150
RO
RO
31
15
0
0
31:1
0
Register 28: Clock Verification Clear (CLKVCLR), offset 0x150
This register is provided as a means of clearing the clock verification circuits by software. Since
the clock verification circuits force a known good clock to control the process, the controller is
allowed the opportunity to solve the problem and clear the verification fault. This register clears all
clock verification faults. To clear a clock verification fault, the VERCLR bit must be set and then
cleared by software. This bit is not self-clearing.
RO
RO
30
14
0
0
Reserved
VERCLR
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
Clear clock verification faults.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S101 Data Sheet
RO
RO
18
0
2
0
RO
RO
17
0
1
0
VERCLR
R/W
RO
16
0
0
0
78
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