LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 97
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 97 of 284
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General-Purpose Input/Outputs (GPIOs)
8.2.5
8.2.6
8.3
97
Pad Configuration
The pad configuration registers allow for GPIO pad configuration by software based on the
application requirements. The pad configuration registers include the GPIODR2R, GPIODR4R,
GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers
as well as the GPIOPCellID0-GPIOPCellID3 registers.
Initialization and Configuration
On reset, all GPIO pins (except for the five JTAG pins) default to general-purpose input mode
(GPIODIR and GPIOAFSEL both set to 0). Table 8-1 shows all possible configurations of the
GPIO pads and the control register settings required to achieve them. Table 8-2 shows how a
rising edge interrupt would be configured for pin 2 of a GPIO port.
Table 8-1.
a. X=Ignored (don’t care bit)
Digital Input (GPIO)
Digital Output (GPIO)
Open Drain Input (GPIO)
Open Drain Output (GPIO)
Analog Input (Comparator)
Digital Output (Comparator)
Digital Input/Output (UART)
Digital Input/Output (SSI)
Digital Output (Timer PWM)
Digital Input (Timer CCP)
?=Can be either 0 or 1, depending on the configuration
Configuration
Pad Configuration Examples
0
0
0
0
0
1
1
1
1
1
Preliminary
X
X
X
X
X
0
1
0
1
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
Register Bit Value
X
X
?
?
0
?
?
?
?
?
X
X
?
?
0
?
?
?
?
?
a
X
X
X
X
?
?
?
?
?
?
X
X
X
X
?
?
?
?
?
?
March 22, 2006
X
X
X
X
?
?
?
?
?
?
X
X
X
X
?
?
?
?
?
?
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