LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 203
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
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Universal Asynchronous Receiver/Transmitter (UART)
203
Reset
Reset
Type
Type
UART Raw Interrupt Status (UARTRIS)
Offset 0x03C
31:11
RO
RO
31
15
0
0
3:0
Bit
10
9
8
7
6
5
4
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
RO
RO
30
14
0
0
reserved
reserved
OERIS
BERIS
PERIS
RXRIS
FERIS
RTRIS
TXRIS
Name
reserved
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
OERIS
RO
RO
26
10
0
0
Reset
0xF
0
0
0
0
0
0
0
0
BERIS
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
This reserved bit is read-only.
PERIS
RO
RO
24
0
8
0
reserved
FERIS
RO
RO
23
0
7
0
RTRIS
RO
RO
22
0
6
0
TXRIS
RO
RO
21
0
5
0
RXRIS
RO
RO
20
0
4
0
RO
RO
19
0
3
1
RO
RO
18
0
2
1
reserved
March 22, 2006
RO
RO
17
0
1
1
RO
RO
16
0
0
1
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