LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 108
![no-image](/images/no-image-200.jpg)
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 108 of 284
- Download datasheet (3Mb)
March 22, 2006
Reset
Reset
Type
Type
GPIO Interrupt Clear (GPIOICR)
Offset 0x41C
RO
RO
31
15
0
0
31:8
7:0
Bit
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
RO
RO
30
14
0
0
reserved
Name
IC
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
W1C
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0x00
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPIO Interrupt Clear
0: Corresponding interrupt is unaffected.
1: Corresponding interrupt is cleared.
RO
RO
24
0
8
0
reserved
W1C
RO
23
0
7
0
W1C
RO
22
0
6
0
W1C
RO
21
0
5
0
W1C
RO
20
0
4
0
IC
W1C
RO
19
0
3
0
LM3S101 Data Sheet
W1C
RO
18
0
2
0
W1C
RO
17
0
1
0
W1C
RO
16
0
0
0
108
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