LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 130

• Manufacturer Part Number: LM3S328-IQC20-A0
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

General-Purpose Input/Outputs (GPIOs)
130
Reset
Reset
Type
Type
Bit/Field
31:8
GPIO 2-mA Drive Select (GPIODR2R)
Offset 0x500
7:0
RO
RO
31
15
0
0
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the
port to be individually configured without affecting the other pads. When writing a DRV2 bit for a
GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the
GPIODR8R register are automatically cleared by hardware.
RO
RO
30
14
0
0
reserved
Name
DRV2
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0xFF
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
Output Pad 2-mA Drive Enable
A write of 1 to either
corresponding 2-mA enable bit. The change is effective on the
second clock cycle after the write.
RO
RO
24
0
8
0
reserved
R/W
RO
23
0
7
1
R/W
RO
22
0
6
1
GPIODR4
R/W
RO
21
0
5
1
R/W
RO
20
0
4
1
[n] or
DRV2
R/W
RO
GPIODR8
19
0
3
1
R/W
RO
18
0
2
1
[n] clears the
April 27, 2007
R/W
RO
17
0
1
1
R/W
RO
16
0
0
1