LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 316

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LM3S328-IQC20-A0

Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
Inter-Integrated Circuit (I2C) Interface
Figure 14-13. Slave Command Sequence
14.2.2
316
Available Speed Modes
The SCL clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and
SCL_HP.
where:
CLK_PRD
SCL_LP
SCL_HP
TIMER_PRD
page 326).
The SCL clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
is the Low phase of the SCL clock (fixed at 6)
is the High phase of the SCL clock (fixed at 4)
is the system clock period
is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
NO
TREQ bit=1?
Write data to
I2CSDR
YES
Preliminary
NO
Write OWN Slave
also valid
Write ------- 1
Read I2CSCSR
FBR is
Read data from
RREQ bit=1?
to I2CSCSR
Address to
I2CSOAR
I2CSDR
Idle
YES
April 27, 2007

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