LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 302

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LM3S328-IQC20-A0

Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
Synchronous Serial Interface (SSI)
302
Reset
Type
Reset
Type
Bit/Field
SSI Primecell Identification 0 (SSIPCellID0)
Offset 0xFF0
31:8
7:0
RO
RO
31
15
0
0
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
RO
RO
30
14
0
0
reserved
Name
CID0
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
RO
RO
27
11
RO
RO
0
0
RO
RO
26
10
0
0
Reset
0x0D
RO
RO
25
0
0
9
0
Preliminary
RO
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification
system.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
CID0
RO
RO
19
0
3
1
RO
RO
18
0
2
1
April 27, 2007
RO
RO
17
0
1
0
RO
RO
16
0
0
1

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