LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 182
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LM3S328-IQC20-A0
Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S328-IQC20-A0.pdf
(371 pages)
- Current page: 182 of 371
- Download datasheet (3Mb)
Watchdog Timer
10
10.1
Figure 10-1. WDT Module Block Diagram
182
System Clock
Interrupt
Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first
time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has
been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
Block Diagram
Control / Clock /
Generation
WDTLOCK
WDTTEST
WDTCTL
Interrupt
WDTICR
WDTMIS
WDTRIS
WDTPCellID0
WDTPCellID1
WDTPCellID2
WDTPCellID3
Identification Registers
Preliminary
WDTPeriphID0
WDTPeriphID1
WDTPeriphID2
WDTPeriphID3
0x00000000
WDTPeriphID4
WDTPeriphID5
WDTPeriphID6
WDTPeriphID7
32-Bit Down
Comparator
WDTLOAD
Counter
WDTVALUE
April 27, 2007
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