Z86D99 ZILOG [Zilog, Inc.], Z86D99 Datasheet - Page 50

• Manufacturer Part Number: Z86D99
• Description: Low-Voltage Micro controllers with ADC
• Manufacturer: ZILOG [Zilog, Inc.]

PS003807-1002
T
gate
IN
T
IN
clock
P5
OSC
2
Each High-to-Low transition on T
of the selected T
be masked or enabled according to the needs of the application.
External Clock Input Mode
The T
the counting of external events, where an event is considered to be a High-to-Low
transition on T
occurrence (continuous mode) of that event.
Figure 30. External Clock Input Mode
Gated Internal Clock Mode
The T
tively) measures the duration of an external event. In this mode, the T
is driven by the internal timer clock, gated by a High level on T
T
IRQ
gate input. Interrupt request IRQ
Figure 31. Gated Clock Input Mode
1
counts while T
0
is generated on the High-to-Low transition of T
IN
IN
External Clock Input mode (TMR bits D
Gated Internal Clock mode (TMR bits D
Internal clock
D
P5
+2
2
IN
IN
(see Figure 30) occurrence (single-pass mode) or on every nth
IN
P
D
mode or the enabled/disabled state of T
is High and stops counting when T
R
TMR
D
5
–D
E
4
D
L
= 01
I
5
IN
is generated if T
M
generates interrupt request IRQ
Z86D990/Z86D991 OTP and Z86L99X ROM
D
I
Low-Voltage Microcontrollers with ADC
Internal clock
N
+4
TMR
D
5
–D
A
5
4
5
R
and D
= 00
and D
1
reaches its end-of-count.
IN
Y
PRE1
, signaling the end of the
IN
4
PRE1
4
both set to
is Low. Interrupt request
set to
1
. IRQ
IN
T1
0
(see Figure 31).
0
and
T1
must therefore
0
0
, regardless
) supports
1
1
, respec-
prescaler
IRQ5
IRQ5
IRQ0
IRQ0
43