Z86D99 ZILOG [Zilog, Inc.], Z86D99 Datasheet - Page 90

• Manufacturer Part Number: Z86D99
• Description: Low-Voltage Micro controllers with ADC
• Manufacturer: ZILOG [Zilog, Inc.]

PS003807-1002
Bit
Bit/Field
R/W
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
7_______
_6______
__5_____
___432__
_______10
Stop-Mode Recovery Register
The SMR register serves two functions. Bit D7 of the SMR register, as shown in
Table 50, is the Stop Mode Flag that is set upon entering stop mode. A 0 in this bit
indicates that the device has been reset by a POR or WDT Reset. A POR or WDT
Reset is sometimes referred to as a “cold” start. A 1 in bit D7 indicates that the
device was awakened by a SMR source. Waking a device with a SMR source is
sometimes referred to as a “warm” start.
The Stop Mode Recovery source can be selected by any combination of P2 and
P5 by P2SMR and P5SMR, respectively. If the pin is selected as the SMR source,
its logic level is latched into a register. A wait up signal is generated if its logic level
changes. This applies to all selected pins for the SMR source.
The comparators of P5 cannot be used as an SMR source. The comparator is
turned off in STOP mode.
Table 50. SMR Register (Group/Bank 0Fh, Register B)
The second function of the SMR register is the selection of the external clock
divide value. The purpose of this control is to selectively reduce device power
7
Stop
Flag
R
0
Bit/Field
Stop Mode Flag
Reserved
Stop Delay
Reserved
System Clock
Select
P
6
Re-
served
R/W
0
R
E
L
5
Stop
Delay
W
1
R/W
R
R
W
R
W
R
W
W
R
W
R
W
W
W
W
I
M
Z86D990/Z86D991 OTP and Z86L99X ROM
4
Reserved
R/W
0
Value
1
0
X
1
X
1
1
0
1
X
11
11
10
01
00
I
Low-Voltage Microcontrollers with ADC
N
A
3
R/W
0
Description
Stop Recovery (warm start)
POR/WDT Reset (cold start)
No Effect
Always reads 1
No Effect
Always reads 1
Enable 5ms /Reset delay
Disable /Reset delay after SMR
Always reads 111
No Effect
Always reads 11
SCLK, TCLK = XTAL/16
SCLK, TCLK = XTAL
SCLK, TCLK = XTAL/32
SCLK, TCLK = XTAL/2
R
Y
2
R/W
0
1
SCLK Select
W
0
0
W
0
83