TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 14

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
Figure 2.1. is a functional block diagram of TSC80251 microcontrollers. The core, which is common to all TSC80251
microcontrollers, is described in the next paragraph. Each derivative in the family has its own on–chip peripherals, I/O
Ports, external bus, size of on–chip RAM, type and size of on–chip ROM.
2.2. Microcontroller Core
The TSC80251 microcontroller core contains the CPU, the clock and reset unit, the interrupt handler, the bus interface
and the peripheral interface (See Figure 2.1. ). The CPU contains the instruction sequencer, ALU, register file and data
memory interface (See Figure 2.2. ).
2.2.1. CPU
The TSC80251 fetches instructions from on–chip code memory two bytes at a time or from external memory one byte
at a time. The instructions are sent over the 16–bit instruction bus to the CPU. You can configure the TSC80251 to
operate in page mode for accelerated instruction fetches from external memory. In page mode, if an instruction fetch
is to the same 256–byte “page” as the previous fetch, the fetch requires one state (two clocks) rather than two states
(four clocks). For information regarding the page or non–page mode selection, see Product Design Guide.
The TSC80251 register file has 40 registers, which can be accessed as bytes (8–bit data), words (16–bit data) and double
words (32–bit data). As in the C51 Architecture, registers 0-7 consist of four banks of eight registers each, where the
active bank is selected by the Program Status Word (PSW) for fast context switches (See “Programming” chapter).
2.2
PORTS
CPU
Bus Interface Unit
OTPROM
EPROM
ROM
16–bit Memory Address
16–bit Memory Code
Figure 2.1. TSC80251 Product Block Diagram
RAM
Interrupt Handler Unit
Peripherals
Clock
Reset
Rev. C – May 7, 1999