TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 36

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. C – May 7, 1999
4.6. Control Instructions
Control instructions “instructions that change program flow” include calls, returns, and conditional and unconditional
jumps (See Table 5.27). Instead of executing the next instruction in the queue, the processor executes a target
instruction. The control instruction provides the address of a target instruction either implicitly, as in a return from a
subroutine, or explicitly, in the form of a relative, direct, or indirect address.
TSC80251 microcontrollers have a 24–bit program counter (PC), which allows a target instruction to be anywhere in
the 16–Mbyte address space. however, as discussed in this section, some control instructions restrict the target address
to the current 2–Kbyte or 64–Kbyte address range by allowing only the lowest 11 or lowest 16 bits of the program
counter to change.
4.6.1. Addressing Modes for Control Instructions
Table 4.10. lists the addressing modes for the control instructions.
C251 (bi )
C251 (bit)
C51 (bi )
C51 (bit)
Architecture
Relative addressing:
The control instruction provides the target address as an 8–bit signed offset (rel) from the address of the next
instruction.
Direct addressing:
The control instruction provides a target address, which can have 11 bits (addr11), 16 bits (addr16), or 24 bits
(addr24). The target address is written to the PC.
Indirect addressing:
There are two types of indirect addressing for control instructions:
addr11: Only the lower 11 bits of the PC are changed; i.e., the target address must be in the current 2–Kbyte
block (the 2–Kbyte block that includes the first byte of the next instruction).
addr16: Only the lower 16 bits of the PC are changed; i.e., the target address must be in the current 64–Kbyte
region (the 64–Kbyte region that includes the first byte of the next instruction).
addr24: The target address can be anywhere in the 16–Mbyte address space.
For the instructions LCALL @WRj and LJMP @WRj, the target address is in the current 64–Kbyte region. The
16–bit address in WRj is placed in the lower 16 bits of the PC. The upper eight bits of the PC remain unchanged
from the address of the next instruction.
For the instruction JMP @A+DPTR, the sum of the accumulator and DPTR is placed in the lower 16 bits of
the PC, and the upper eight bits of the PC are FF:, which restricts the target address to the code memory space
of the C51 Architecture.
Memory
SFR
Memory
SFR
Variants
Table 4.9. Addressing Modes for Bit Instructions
NA
NA
00h-7Fh
80h-F8h
Bit Address
20h.0-7Fh.7
All defined SFRs
20h.0-7Fh.7
XXh.0-XXh.7, where XX =
80, 88, 90, 98, ..., F0, F8
Memory/SFR Address
SFRs are not defined at all
bit-addressable locations
TSC80251
Comments
4.11