TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 18

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
3.2. C51 Architecture Address Spaces
Figure 3.2. shows the address spaces of the C51 Architecture. Internal data memory locations 00h-7Fh can be
addressed directly, indirectly by register addressing mode and bit addressing mode for data locations 20h–2Fh. Internal
data locations 80h-FFh can only be addressed indirectly. Directly addressing these locations accesses the SFRs. The
64–Kbyte code memory has a separate memory space. Data in the code memory can be accessed only with the MOVC
instruction. Similarly, the 64–Kbyte external data memory can be accessed only with the MOVX instruction.
The register file (registers R0-R7) comprises four, switchable register banks, each having 8 registers. The 32 bytes
required for the four banks occupy locations 00h-1Fh in the on–chip data memory.
3.3. C51 Architecture mapping to C251 Architecture Address Spaces
The 64–Kbyte code memory for 80C51 microcontrollers maps into region FF: of the memory space for TSC80251
microcontrollers. Assemblers for TSC80251 microcontrollers assemble code for 80C51 microcontrollers into region
FF:, and data accesses to code memory (MOVC) are directed to this region. The assembler also maps the interrupt
vectors to region FF:. This mapping is transparent to the user; code executes just as with a 80C51 micro without
modification.
3.2
(direct, indirect)
Internal Data
Figure 3.2. Address Spaces for the C51 Architecture
0000h
0000h
80h
30h
20h
18h
0Fh
08h
00h
External Data
Internal Data
(indirect)
(MOVX)
(MOVC)
R0–R7
R0–R7
R0–R7
R0–R7
Code
FFFFh
FFFFh
FFh
7Fh
2Fh
1Fh
17h
0Eh
07h
80h
bit addressable
register addressable
(direct)
SFRs
FFh
Rev. C – May 7, 1999