TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 58

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. C – May 7, 1999
Notes:
1.
2.
3.
Exchange bytes
Exchange Digit
Push
Pop
XCH
XCHD
PUSH
PUSH
POP
POP
Mnemonic
Mnemonic
A shaded cell denotes an instruction in the C51 Architecture.
If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
A, Rn
A, dir8
A, @Ri
A, @Ri
dir8
#data
#data16
Rm
WRj
DRk
dir8
Rm
WRj
DRk
<src>
<dest>,
<dest>,
(1)
Table 5.17. Summary of Exchange, Push and Pop Instructions
XCH A, <src>
XCHD A, <src>
PUSH <src>
POP <dest>
ACC and register
ACC and direct address (on–chip RAM or
SFR)
ACC and indirect address
ACC low nibble and indirect address (256
bytes)
Push direct address onto stack
Push immediate data onto stack
Push 16-bit immediate data onto stack
Push byte register onto stack
Push word register onto stack
Push double word register onto stack
Pop direct address (on–chip RAM or SFR)
from stack
Pop byte register from stack
Pop word register from stack
Pop double word register from stack
Comments
Comments
(A)
(A)
(SP)
(SP)
(SP)
dest opnd
3:0
src opnd
(SP) +1; ((SP))
(SP) + size (src opnd) – 1
(SP) – size (dest opnd) + 1;
Bytes
src opnd
Binary Mode
1
2
1
1
2
4
5
3
3
3
2
3
3
3
((SP)); (SP)
TSC80251
3:0
States
3
2
3
3
(3)
4
4
(2)
4
5
4
5
9
(2)
3
5
9
src opnd;
Bytes
(SP) –1
Source Mode
2
2
2
2
2
3
4
2
2
2
2
2
2
2
States
3
2
3
4
(3)
5
5
(2)
3
5
3
4
8
(2)
2
4
8
5.13