TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 49

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
5.1.2. Size and Execution Time for Instruction Families
Notes:
1.
2.
3.
4.
5.4
Add
Subtract
Add with Carry
Subtract with Borrow
ADD
ADD
ADD /
ADD /
SUB
ADDC /
SUBB
SUBB
Mnemonic
Mnemonic
A shaded cell denotes an instruction in the C51 Architecture.
If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
A, Rn
A, dir8
A, @Ri
A, #data
Rmd, Rms
WRjd, WRjs
DRkd, DRks
Rm, #data
WRj, #data16
DRk, #0data16
Rm, dir8
WRj, dir8
Rm, dir16
WRj, dir16
Rm, @WRj
Rm, @DRk
A, Rn
A, dir8
A, @Ri
A, #data
<src>
<dest>,
<dest>,
(1)
Table 5.7. Summary of Add and Subtract Instructions
ADD <dest>, <src>
SUB <dest>, <src>
ADDC <dest>, <src>
SUBB <dest>, <src>
Register to ACC
Direct address to ACC
Indirect address to ACC
Immediate data to ACC
Byte register to/from byte register
Word register to/from word register
Dword register to/from dword register
Immediate 8-bit data to/from byte register
Immediate 16-bit data to/from word register
16-bit unsigned immediate data to/from
dword register
Direct address (on–chip RAM or SFR)
to/from byte register
Direct address (on–chip RAM or SFR)
to/from word register
Direct address (64K) to/from byte register
Direct address (64K) to/from word register
Indirect address (64K) to/from byte register
Indirect address (16M) to/from byte register
Register to/from ACC with carry
Direct address (on–chip RAM or SFR)
to/from ACC with carry
Indirect address to/from ACC with carry
Immediate data to/from ACC with carry
Comments
Comments
dest opnd
dest opnd
(A)
(A)
(A) + src opnd + (CY)
(A) – src opnd – (CY)
Bytes
Binary Mode
1
2
1
2
3
3
3
4
5
5
4
4
5
5
4
4
1
2
1
2
dest opnd + src opnd
dest opnd – src opnd
States
1
3
3
4
3
4
1
1
2
1
2
3
5
3
4
6
4
1
2
1
(2)
(2)
(3)
(4)
(3)
(3)
(2)
Rev. C – May 7, 1999
Bytes
Source Mode
2
2
2
2
2
2
2
3
4
4
3
3
4
4
3
3
2
2
2
2
States
1
2
2
3
2
3
1
2
3
1
1
2
4
2
3
5
3
2
3
1
(2)
(2)
(3)
(4)
(3)
(3)
(2)