SX18AA100-I/DP ETC [List of Unclassifed Manufacturers], SX18AA100-I/DP Datasheet - Page 13

• Manufacturer Part Number: SX18AA100-I/DP
• Description: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug
• Manufacturer: ETC [List of Unclassifed Manufacturers]

5.0 DEVICE CONFIGURATION REGISTERS
The SX device has three registers (FUSE, FUSEX,
DEVICE) that control functions such as operating the
device in Turbo mode, extended (8-level deep) stack
operation, and speed selection for the internal RC oscilla-
tor. These registers are not programmable “on the fly”
5.1 FUSE Word (Read/Program at FFFh in main memory map)
© 2000 Scenix Semiconductor, Inc. All rights reserved.
TURBO
SYNC
IRC
DIV1: DIV0
IFBD
CP
WDTE
FOSC2: FOSC0 External oscillator configuration (valid when IRC = 1):
TURBO
Bit 11
SYNC
Turbo mode enable:
0 =
1 =
Synchronous input enable (for turbo mode): This bit synchronizes the signal presented at the input pin
to the internal clock through two internal flip-flops.
0 =
1 =
0 =
1 =
00b
01b
10
11b
Internal crystal/resonator oscillator feedback resistor:
0=
1=
Code protect enable:
0 =
1 =
Watchdog timer enable:
0 =
1 =
000b = LP1 – low power crystal (32KHz)
001b = LP2 – low power crystal/resonator (32 KHz to 1 MHz)
010b = XT1 – normal crystal/resonator (32 KHz to 10 MHz)
011b = XT2 – normal crystal/resonator (1MHz to 24 MHz)
100b = HS1 – high speed crystal/resonator (1MHz to 50 MHz)
101b = HS2 – high speed crystal/resonator (1 MHz to 50 MHz)
110b = HS3 – high speed crystal/resonator (1 MHz to 50 MHz)
111b = RC network - OSC2 is pulled high with a weak pullup (no CLKOUT output)
Note:
Internal RC oscillator enable:
Internal RC oscillator divider:
Reserved
enabled
disabled
enabled - OSC1 pulled low by weak pullup, OSC2 pulled high by weak pullup
disabled - OSC1 and OSC2 behave according to FOSC2: FOSC0
=
=
=
=
disabled
enabled
enabled (FUSE, code, and ID memories read back as garbled data)
disabled (FUSE, code, and ID memories can be read normally)
disabled
enabled
The frequencies are target values.
turbo (instruction clock = osc/1)
instr clock = osc/4
Reserved
4 MHz
1 MHz
128 KHz
32 KHz
Internal feedback resistor disable (external feedback required)
Internal feedback resistor enabled (valid when IRC = 1)
IRC
DIV1/
IFBD
- 13 -
during normal device operation. Instead, the FUSE and
FUSEX registers can only be accessed when the SX
device is being programmed. The DEVICE register is a
read-only, hard-wired register, programmed during the
manufacturing process.
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
FOSC2
DIV0/
served
Re-
CP
WDTE
FOSC1
www.scenix.com
FOSC0
Bit 0