SX18AA100-I/DP ETC [List of Unclassifed Manufacturers], SX18AA100-I/DP Datasheet - Page 38

• Manufacturer Part Number: SX18AA100-I/DP
• Description: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug
• Manufacturer: ETC [List of Unclassifed Manufacturers]

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
16.1 Equivalent Assembler Mnemonics
Some assemblers support additional instruction mne-
monics that are special cases of existing instructions or
alternative mnemonics for standard ones. For example,
an assembler might support the mnemonic “CLC” (clear
© 2000 Scenix Semiconductor, Inc. All rights reserved.
CLC
CLZ
JMP W
JMP PC+W
MODE imm4
NOT W
SC
SKIP
Note 1: The JMP W or JMP PC+W instruction takes 4 cycles in the “compatible” clocking mode or 3 cycles in the
“turbo” clocking mode.
Note 2: The SC instruction takes 1 cycle if the tested condition is false or 2 cycles if the tested condition is true.
Note 3: The assembler converts the SKIP instruction into a SNB or SB instruction that tests the least significant bit
of the program counter, choosing SNB or SB so that the tested condition is always true. The instruction takes 4 cycles
in the “compatible” clocking mode or 2 cycles in the “turbo” clocking mode.
Syntax
Clear Carry bit
Clear Zero bit
Complement W
Jump Indirect W
Jump Indirect W Relative
Move Immediate to MODE
Register
Skip if Carry bit Set
Skip Next Instruction
Table 16-2. Equivalent Assembler Mnemonics
Description
- 38 -
CLRB $03.0
CLRB $03.2
MOV $02,W
ADD $02,W
MOV M,#lit
XOR W,#$FF
SB $03.0
SNB $02.0 or SB $02.0
carry), which is interpreted the same as the instruction
“clrb $03.0” (clear bit 0 in the STATUS register). Some of
the commonly supported equivalent assembler mnemon-
ics are described in Table 16-2.
Equivalent
4 or 3 (note 1)
4 or 3 (note 1)
1 or 2 (note 2)
4 or 2 (note 3)
Cycles
1
1
1
1
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