SX18AA100-I/DP ETC [List of Unclassifed Manufacturers], SX18AA100-I/DP Datasheet - Page 27

• Manufacturer Part Number: SX18AA100-I/DP
• Description: Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug
• Manufacturer: ETC [List of Unclassifed Manufacturers]

12.0 RESET
Power-On-Reset, Brown-Out reset, watchdog reset, or
external reset initializes the device. Each one of these
reset conditions causes the program counter to branch to
the top of the program memory. For example, on the
device with 2048K words of program memory, the pro-
gram counter is initialized to 07FF.
The device incorporates an on-chip Power-On Reset
(POR) circuit that generates an internal reset as V
during power-up. Figure 12-1 is a block diagram of the
circuit. The circuit contains an 10-bit Delay Reset Timer
(DRT) and a reset latch. The DRT controls the reset time-
out delay. The reset latch controls the internal reset sig-
nal. Upon power-up, the reset latch is set (device held in
reset), and the DRT starts counting once it detects a valid
logic high signal at the MCLR pin. Once DRT reaches the
end of the timeout period (typically 72 msec), the reset
latch is cleared, releasing the device from reset state.
Note:Ripple counter is 10 bits for Power on Reset (POR)
only.
© 2000 Scenix Semiconductor, Inc. All rights reserved.
Figure 12-1. Block Diagram of On-Chip Reset Circuit
V
dd
MCLR/Vpp pin
rc_clk
BROWN-OUT
POR
(DRT Start-Up
10-Bit Asynch
Counter
Ripple
Timer)
POR
wdt_time_out
drt_time
_out
MIWU
S
R
enable
QN
Q
RESET
dd
rises
- 27 -
Figure 12-2 shows a power-up sequence where MCLR is
not tied to the V
and stabilize before MCLR pin is brought high. The
device will actually come out of reset T
MCLR goes high.
The brown-out circuitry resets the chip when device
power (V
not to zero, and then recovers to the normal value.
.
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
Figure 12-2. Time-Out Sequence on Power-Up
drt_time_out
RESET
dd
MCLR
POR
) dips below its minimum allowed value, but
V
dd
(MCLR not tied to V
dd
pin and V
dd
signal is allowed to rise
Tdrt
dd
)
www.scenix.com
drt
msec after