AK4343EN AKM [Asahi Kasei Microsystems], AK4343EN Datasheet - Page 91

• Manufacturer Part Number: AK4343EN
• Description: Stereo DAC with HP/RCV/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
MS0478-E-01
Headphone-amp Output
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4343 is PLL mode, DAC and Speaker-Amp should be
(2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1”
(3) Set up the low frequency boost level (BST1-0 bits)
(4) Set up the ALC Block Digital Volume (Addr: 09H and 0CH)
(5) Set up the output digital volume (Addr: 0AH and 0DH)
(6) Power up DAC and MIN-Amp: PMDAC = PMMIN bits = “0” → “1”
(7) Power up headphone-amp: PMHPL = PMHPR bits = “0” → “1”
(8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1”
(9) Fall down the common voltage of headphone-amp: HPMTN bit = “1” → “0”
(10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0”
(11) Power down DAC and MIN-Amp: PMDAC = PMMIN bits = “1” → “0”
(12) Off the bass boost: BST1-0 bits = “00”
(13) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0”
powered-up in consideration of PLL lock time after a sampling frequency is changed.
AVL7-0 and AVR7-0 bits should be set to “91H”(0dB).
(Addr:05H, D5&D2-0)
(Addr:09H&0CH, D7-0)
(Addr:0AH&0DH, D7-0)
DVL/R7-0 bits
PMHPL/R bits
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1”. The
initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital
data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input
data after the initialization cycle is complete. When ALC bit is “1”, ALC is disable (ALC gain is set by
AVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle,
ALC operation starts from the gain set by AVL/R7-0 bits.
Output voltage of headphone-amp is still HVSS.
The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0µF, the time constant is
If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to
GND, the pop noise occurs. It takes twice of
(Addr:0EH, D3-2)
IVL/R7-0 bits
(Addr:01H, D5-4)
The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0µF, the time constant is
(Addr:0FH, D0)
BST1-0 bits
(Addr:01H, D6)
(Addr:00H, D2)
(Addr:00H, D5)
HPL/R pins
HPMTN bit
PMDAC bit
PMMIN bit
DACH bit
FS3-0 bits
0,000
E1H
18H
00
(1)
Figure 81. Headphone-Amp Output Sequence
(3)
(2)
(4)
(5)
(6)
(7)
(8)
Normal Output
10
1,111
τ
- 91 -
f
that the common voltage goes to GND.
91H
28H
τ
τ
r
f
= 100ms(typ), 250ms(max).
(9)
= 100ms(typ), 250ms(max).
(10)
(11)
(12)
00
(13)
Example:
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
Bass Boost Level : Middle
(1) Addr:05H, Data:27H
(2) Addr:0FH, Data:09H
(5) Addr:0AH&0DH, Data:28H
(6) Addr:00H, Data:64H
(7) Addr:01H, Data:39H
(8) Addr:01H, Data:79H
(9) Addr:01H, Data:39H
(4) Addr:09H&0CH, Data:91H
(10) Addr:01H, Data:09H
(12) Addr:0EH, Data:11H
(13) Addr:0FH, Data:08H
(3) Addr:0EH, Data:19H
(11) Addr:00H, Data:40H
Playback
[AK4343]
2006/10