GAL16LV8C-15LJ LATTICE [Lattice Semiconductor], GAL16LV8C-15LJ Datasheet - Page 18

• Manufacturer Part Number: GAL16LV8C-15LJ
• Description: Low Voltage E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

Circuitry within the GAL16LV8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
Typ. Vref = Vcc
Power-Up Reset
Input/Output Equivalent Schematics
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
Active Pull-up Circuit
(GAL16LV8D Only)
Typical Input
FEEDBACK/EXTERNAL
INTERNAL REGISTER
OUTPUT REGISTER
Vref
Q - OUTPUT
t
pr, 1 s MAX). As a result,
CLK
Vcc
Vcc
Vcc (min.)
Vcc
18
t
pr
conditions must be met to provide a valid power-up reset of the
device. First, the V
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
Typ. Vref = Vcc
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Specifications GAL16LV8
t
wl
Feedback
Tri-State
Control
t
su
CC
rise must be monotonic. Second, the clock
Typical Output
Vcc
Active Pull-up Circuit
(GAL16LV8D Only)
Feedback
(To Input Buffer)
Vref
PIN
PIN
t
pr time.