HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 479
HD6435348R
Manufacturer Part Number
HD6435348R
Description
Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
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2. Mode 2
Figure E-4 shows how the pin states change when the RES pin goes Low during external memory
access in mode 2.
As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS,
DS, RD, and WR signals all go High. The data bus (D
state. Pins P5
*
P1 / ø*
RES
Internal reset signal
A
R/W
AS, RD and DS (read)
WR and DS (write)
D to D (write)
I/O ports
15
7
The dotted line indicates that P1 /ø is an input port if the corresponding DDR bit is 0,
but a clock output pin if the DDR bit is 1.
0
to A
0
7
0
/A
15
to P5
Figure E-1 Reset during Memory Access (Mode 1)
0
/A
8
of the address bus are initialized as input ports.
T
1
External memory access
469
T
2
7
to D
T
3
0
) is placed in the high-impedance
H’0000
High impedance
High impedance
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