HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 5

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

4.9
4.10 Notes on Use of the Stack ····································································································95
Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
5.6
Section 6 Data Transfer Controller
6.1
6.2
6.3
4.8.2 Disabling of Exceptions Immediately after a Reset ··················································92
4.8.3 Disabling of Interrupts after a Data Transfer Cycle ··················································92
Stack Status after Completion of Exception Handling ························································93
4.9.1 PC Value Pushed on Stack for Trace,
4.9.2 PC Value Pushed on Stack for Address Error and Invalid
Overview ······························································································································97
5.1.1 Features ·····················································································································97
5.1.2 Block Diagram ··········································································································98
5.1.3 Register Configuration ······························································································99
Interrupt Types ·····················································································································99
5.2.1 External Interrupts ····································································································99
5.2.2 Internal Interrupts ····································································································101
5.2.3 Interrupt Vector Table ·····························································································102
Register Descriptions ·········································································································104
5.3.1 Interrupt Priority Registers A to F (IPRA to IPRF) ················································104
5.3.2 Timing of Priority Setting ·······················································································105
Interrupt Handling Sequence ·····························································································105
5.4.1 Interrupt Handling Flow ·························································································105
5.4.2 Stack Status after Interrupt Handling Sequence ·····················································108
5.4.3 Timing of Interrupt Exception-Handling Sequence ················································109
Interrupts During Operation of the Data Transfer Controller ············································109
Interrupt Response Time ····································································································112
Overview ····························································································································113
6.1.1 Features ···················································································································113
6.1.2 Block Diagram ········································································································113
6.1.3 Register Configuration ····························································································114
Register Descriptions ·········································································································115
6.2.1 Data Transfer Mode Register (DTMR) ···································································115
6.2.2 Data Transfer Source Address Register (DTSR) ····················································116
6.2.3 Data Transfer Destination Register (DTDR) ·························································116
6.2.4 Data Transfer Count Register (DTCR) ···································································116
6.2.5 Data Transfer Enable Registers A to F (DTEA to DTEF) ······································117
Data Transfer Operation ·····································································································118
6.3.1 Data Transfer Cycle ································································································118
Interrupts, Trap Instructions, and Zero Divide Exceptions ·······································95
Instruction Exceptions ······························································································95