LH28F800 Sharp Electrionic Components, LH28F800 Datasheet - Page 15

• Manufacturer Part Number: LH28F800
• Description: 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
• Manufacturer: Sharp Electrionic Components

set block or permanent lock-bit setup along with
appropriate block or device address is written
followed by either the set block lock-bit confirm (and
an address within the block to be locked) or the set
permanent lock-bit confirm (and any device
address). The WSM then controls the set lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when
read (see Fig. 7). The CPU can detect the
completion of the set lock-bit event by analyzing the
RY/BY# pin output or status register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Permanent Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations
occur only when V
V
bit contents are protected against alteration.
A successful set block lock-bit operation requires
that the permanent lock-bit be cleared and WP# =
V
permanent lock-bit set, SR.1 and SR.4 will be set
to "1" and the operation will fail. Set block lock-bit
operations while V
spurious results and should not be attempted. A
successful set permanent lock-bit operation requires
that RP# = V
SR.1 and SR.4 will be set to "1" and the operation
will fail. Set permanent lock-bit operations with V
< RP# < V
not be attempted.
PPH1/2/3
IH
or RP# = V
. In the absence of this high voltage, lock-
HH
HH
produce spurious results and should
. If it is attempted with RP# = V
HH
. If it is attempted with the
IH
CC
< RP# < V
= V
CC1/2/3/4
HH
and V
produce
PP
IH
IH
=
- 15 -
,
4.10 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the
permanent lock-bit not set and WP# = V
= V
Clear Block Lock-Bits command. If the permanent
lock-bit is set, clear block lock-bits operation is
unable. See Table 5 for a summary of hardware
and software write protection options.
Clear block lock-bits option is executed by a two-
cycle command sequence. A clear block lock-bits
setup is first written. After the command is written,
the device automatically outputs status register data
when read (see Fig. 8). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# pin output or status register
bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bits
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to "1". Also, a reliable clear
block lock-bits operation can only occur when V
V
bits operation is attempted while V
and SR.5 will be set to "1". In the absence of this
high voltage, the block lock-bit contents are
protected against alteration. A successful clear block
lock-bits operation requires that the permanent lock-
bit is not set and WP# = V
attempted with the permanent lock-bit set or WP# =
V
and the operation will fail. A clear block lock-bits
operation with V
results and should not be attempted.
CC1/2/3/4
IL
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
and RP# = V
HH
, block lock-bits can be cleared using the
and V
PP
IH
IH
, SR.1 and SR.5 will be set to "1"
= V
< RP# < V
PPH1/2/3
IH
. In a clear block lock-
or RP# = V
HH
produce spurious
PP
≤ V
PPLK
IH
HH
or RP#
. If it is
, SR.3
CC
=