LH28F800 Sharp Electrionic Components, LH28F800 Datasheet - Page 40

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LH28F800

Manufacturer Part Number
LH28F800
Description
8 M-bit (512 kB x 16) SmartVoltage Flash Memories
Manufacturer
Sharp Electrionic Components
Datasheet

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6.2.7 RESET OPERATIONS
NOTES :
1. These specifications are valid for all product versions
2. If RP# is asserted while a block erase, word write, or
SYMBOL
t
t
t
PLPH
PLRH
235VPH
(packages and speeds).
lock-bit configuration operation is not executing, the reset
will complete within 100 ns.
RY/BY# (R)
RY/BY# (R)
RP# Pulse Low Time (If RP# is tied to V
this specification is not applicable)
RP# Low to Reset during Block Erase,
V
V
V
Word Write or Lock-Bit Configuration
RP# (P)
RP# (P)
RP# (P)
CC
CC
CC
V
2.7 V to RP# High
3.0 V to RP# High
4.5 V to RP# High
CC
V
V
V
V
V
V
V
V
V
V
V
2.7 V/3.3 V/5 V
OH
OL
IH
IL
OH
OL
IH
IL
IL
IH
IL
PARAMETER
Fig. 16 AC Waveform for Reset Operation
t
t
PLPH
PLPH
(A) Reset During Read Array Mode
(B) Reset During Block Erase, Word Write, or Lock-Bit Configuration
(C) V
Reset AC Specifications
CC
t
235VPH
Rising Timing
t
PLRH
CC
,
- 40 -
NOTE
2, 3
4
3. A reset time, t
4. When the device power-up, holding RP#-low minimum
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
or RP# going high until outputs are valid.
100 ns is required after V
range and also has been in stable there.
V
MIN.
(NOTE 1)
CC
100
100
= 2.7 to 3.6 V
28 (2.7 V V
PHQV
MAX.
20
, is required from the latter of RY/BY#
CC
)
CC
V
MIN.
100
100
CC
has been in predefined
= 5.0±0.5 V
MAX.
12
UNIT
ns
µs
ns

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