LH28F800 Sharp Electrionic Components, LH28F800 Datasheet - Page 24

• Manufacturer Part Number: LH28F800
• Description: 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
• Manufacturer: Sharp Electrionic Components

5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Three-
line control provides for :
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 RY/BY# and Block Erase, Word Write,
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, word
write and lock-bit configuration completion. It
transitions low after block erase, word write, or lock-
bit configuration commands and returns to V
when the WSM has finished executing the internal
algorithm.
RY/BY# can be connected to an interrupt input of
the system CPU or controller. It is active at all
times. RY/BY# is also V
block erase suspend (with word write inactive),
word write suspend or deep power-down modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics
require
designers are interested in three supply current
a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention
will not occur.
and Lock-Bit Configuration Polling
careful
device
OH
when the device is in
decoupling.
System
OH
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issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its V
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between V
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4 V
Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the V
trace. The V
for word writing and block erasing. Use similar trace
widths and layout considerations given to the V
power bus. Adequate V
decoupling will decrease V
overshoots.
5.5 V
Block erase, word write and lock-bit configuration
are not guaranteed if V
V
V
is detected, status register bit SR.3 is set to "1"
along with SR.4 or SR.5, depending on the
attempted operation. If RP# transitions to V
block erase, word write, or lock-bit configuration,
RY/BY# will remain low until the reset operation is
complete. Then, the operation will abort and the
device will enter deep power-down. The aborted
operation may leave data partially altered.
Therefore, the command sequence must be
PPH1/2/3
CC1/2/3/4
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
PP
CC
range, or RP# ≠ V
range, V
, V
Trace on Printed Circuit Boards
PP
CC
PP
pin supplies the memory cell current
, RP# Transitions
and GND and between its V
CC
PP
falls outside of a valid
PP
falls outside of a valid
PP
IH
supply traces and
voltage spikes and
or V
PP
HH
power supply
. If V
IL
PP
during
error
CC
CC
PP