XC68HC05P18A Motorola, XC68HC05P18A Datasheet
XC68HC05P18A
Related parts for XC68HC05P18A
XC68HC05P18A Summary of contents
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MC68HC05P18A HCMOS Microcontroller Unit TECHNICAL DATA Order this document by MC68HC05P18A/D ...
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... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended ...
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... Section 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . 49 Section 7. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . 55 Section 8. 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Section 9. Serial Input/Output Ports (SIOP Section 10. EEPROM Section 11. Analog-to-Digital (A/D) Converter . . . . . . . . 91 Section 12. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . 97 Section 13. Electrical Specifications . . . . . . . . . . . . . . . 115 Section 14. Mechanical Specifications . . . . . . . . . . . . . 125 Section 15. Ordering Information . . . . . . . . . . . . . . . . . 127 MC68HC05P18A MOTOROLA List of Sections List of Sections Technical Data 3 ...
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... List of Sections Technical Data 4 List of Sections MC68HC05P18A MOTOROLA ...
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... MC68HC05P18A MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Power Supply (V and V DD Oscillator Pins (OSC1 and OSC2 .20 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Reset (RESET .22 Port A (PA0–PA7 .22 Port B (PB5/SDO, PB6/SDI, and PB7/SCK .23 Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/V Port D (PD5/CKOUT and PD7/TCAP) ...
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... Software Interrupt (SWI .42 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 External Interrupt (IRQ .43 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .44 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .44 Section 5. Resets Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 External Reset (RESET .46 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Power-On Reset (POR .47 Computer Operating Properly (COP) Reset . . . . . . . . . . . . .47 Low-Voltage Reset (LVR .48 Table of Contents MC68HC05P18A MOTOROLA ...
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... MC68HC05P18A MOTOROLA Section 6. Operating Modes Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Halt Mode .53 WAIT Instruction .53 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .54 Section 7. Input/Output (I/O) Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port .56 Port .57 Port .58 Port .59 I/O Port Programming .60 Section 8. 16-Bit Timer Contents ...
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... Section 11. Analog-to-Digital (A/D) Converter Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Reference Supply Voltage (V Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Digital Section .93 Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . .93 Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .94 A/D Status and Control Register .94 A/D Conversion Value Data Register . . . . . . . . . . . . . . . . . . . .96 Table of Contents ) . . . . . . . . . . . . . . . . . . .92 REFH MC68HC05P18A MOTOROLA ...
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... MC68HC05P18A MOTOROLA A/D Subsystem Operation during Wait Mode and Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 A/D Subsystem Operation during Stop Mode .96 Section 12. Instruction Set Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Immediate .99 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Indexed, 8-Bit Offset .100 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Register/Memory Instructions ...
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... Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 14.1 14.2 14.3 14.4 15.1 15.2 15.3 Technical Data 10 Section 14. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 28-Pin Plastic Dual In-Line Package (Case #710 .126 28-Pin Small Outline Package (Case #751F .126 Section 15. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Table of Contents MC68HC05P18A MOTOROLA ...
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... MC68HC05P18A MOTOROLA Title MC68HC05P18A Block Diagram . . . . . . . . . . . . . . . . . . . . . . .17 User Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 MC68HC05P18A User Mode Memory Map . . . . . . . . . . . . . . .27 MC68HC05P18A I/O and Control Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Accumulator ( .35 Index Register (X .35 Stack Pointer (SP .36 Program Counter (PC .36 Condition Code Register (CCR .37 Interrupt Processing Flowchart ...
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... Output Compare Registers (OCRH/OCRL .68 Output Compare Software Initialization Example . . . . . . . . . . .69 Input Capture Registers (ICRH/ICRL .70 State Timing Diagram for Input Capture . . . . . . . . . . . . . . . . . .71 SIOP Block Diagram .78 SIOP Timing Diagram .79 SIOP Control Register (SCR .80 SIOP Status Register (SSR .82 SIOP Data Register (SDR .83 List of Figures Page MC68HC05P18A MOTOROLA ...
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... Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .105 12-4 Bit Manipulation Instructions .106 12-5 Control Instructions .107 12-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 12-7 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 15-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 MC68HC05P18A MOTOROLA Title Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . . .40 COP Watchdog Timer Recommendations . . . . . . . . . . . . . . . .54 Port A I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Port B I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Port C I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Port D I/O Pin Functions ...
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... List of Tables Technical Data 14 List of Tables MC68HC05P18A MOTOROLA ...
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... MC68HC05P18A MOTOROLA Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Power Supply (V and V DD Oscillator Pins (OSC1 and OSC2 .20 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Reset (RESET .22 Port A (PA0–PA7 .22 Port B (PB5/SDO, PB6/SDI, and PB7/SCK .23 Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/V Port D (PD5/CKOUT and PD7/TCAP) ...
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... General Description 1.2 Introduction The Motorola MC68HC05P18A is a low-cost microcontroller with: • • • • The HC05 central processor unit (CPU) core contains: • • • • This device is available in: • • A functional block diagram of the MC68HC05P18A is shown in Figure Technical Data 16 4-channel, 8-bit analog-to-digital (A/D) converter ...
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... PB5/SDO SIOP PB6/SDI REGISTERS AND LOGIC PB7/SCK Figure 1-1. MC68HC05P18A Block Diagram NOTE: A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. MC68HC05P18A MOTOROLA COP ALU ACCUMULATOR INDEX REGISTER STK PNTR ...
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... I/O lines and 1 input-only line Individually mask selectable pullups/interrupts on port A pins High current sink and source on two I/O pins, PC0 and PC1 Power-saving stop mode and wait mode instructions and stop conversion to halt mode (mask option) Mask option for clock output pin General Description MC68HC05P18A MOTOROLA ...
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... This subsection describes the functionality of each pin on the MC68HC05P18A package. NOTE: For pins connected to subsystems described in other sections, a reference to the section is given instead of a detailed functional description. The pinout is shown in MC68HC05P18A MOTOROLA first 256 eight port A pins Figure 1-2. General Description General Description ...
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... PA2 8 PA1 9 PA0 10 SDO/PB5 11 SDI/PB6 12 SCK/PB7 Figure 1-2. User Mode Pinout ) SS is connected to ground. SS General Description OSC1 26 OSC2 25 PD7/TCAP 24 TCMP 23 PD5/CKOUT 22 PC0 21 PC1 20 PC2 19 PC3/AD3 18 PC4/AD2 17 PC5/AD1 16 PC6/AD0 15 PC7/V REFH and connected Figure 1-3 (a) Figure 1-3 (b) MC68HC05P18A MOTOROLA ...
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... The load capacitance values used in the oscillator circuit design should include all stray capacitances. Mount the crystal and components as close as possible to the pins for startup stabilization and to minimize output distortion. MC68HC05P18A MOTOROLA , of the oscillator or external clock source is divided OSC STOP ...
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... A lines are configured as inputs during power-on or reset. Eight mask options can be chosen to enable pullups and interrupts (active low) on port A pins (see Options). Refer to Interrupts. Technical Data 22 Figure 1-3 (a) can be used for a ceramic Figure 1-3 (b). Section 5. Resets. Section 7. Input/Output (I/O) Ports General Description 1.4 Mask and Section 4. MC68HC05P18A MOTOROLA ...
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... D function must be chosen with the mask option and is not alterable in software. 1.5.8 Timer Output Compare (TCMP) TCMP is the output from the 16-bit timer’s output compare function low after reset. Refer to MC68HC05P18A MOTOROLA Section 7. Input/Output (I/O) Ports (SIOP). Section 7. Input/Output (I/O) and Section 8. 16-Bit Section 8 ...
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... Schmitt trigger as part of its input circuitry to improve noise immunity. Refer to 1.5.10 CPU Core The MC68HC05P18A uses a standard M68HC05 series CPU core. A description of the instruction set is in Technical Data 24 time period. ILIH DD Section 4. Interrupts. Section 12. Instruction General Description for a wired-OR operation. supply. The IRQ pin DD Set. MC68HC05P18A MOTOROLA ...
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... Introduction The MC68HC05P18A utilizes 14 address lines to access an internal memory space covering 16 Kbytes. This memory space is divided into: • • • • MC68HC05P18A MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Input/output (I/O) Random-access memory (RAM) Electrically erasable programmable read-only memory ...
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... Reading unimplemented bits returns unknown states, and writing unimplemented bits is ignored. Technical Data 26 32 bytes of I/O 192 bytes of RAM 128 bytes of EEPROM 8000 bytes of user ROM 48 bytes of user page zero ROM 16 bytes of user vector ROM 2-1. and Figure 2-3 briefly describe the I/O and control registers Memory Map MC68HC05P18A MOTOROLA ...
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... MC68HC05P18A MOTOROLA 0000 I/O 32 BYTES 0031 0032 USER ROM 48 BYTES 0079 0080 INTERNAL RAM 192 BYTES 0191 0192 STACK 64 BYTES 0255 0256 0271 0272 ...
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... Figure 2-2. MC68HC05P18A I/O and Control Registers Memory Map Memory Map $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F MC68HC05P18A MOTOROLA ...
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... See page 57. Port C Data Direction $0006 (DDRC) See page 58. Port D Data Direction $0007 (DDRD) See page 59. $0008 Unimplemented Figure 2-3. I/O and Control Registers (Sheet MC68HC05P18A MOTOROLA Bit Read: PA7 PA6 PA5 Write: Reset: Read: PB7 PB6 PB5 Write: ...
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... ICRH6 ICRH5 ICRH4 Unaffected by reset = Unimplemented R Memory Map Bit SDR3 SDR2 SDR1 SDR0 IEDG OLVL ICRH3 ICRH2 ICRH1 ICRH0 = Reserved U = Unaffected MC68HC05P18A MOTOROLA ...
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... Alternate Counter Register $001B (ACRL) See page 66. EEPROM Programming $001C Register (EEPROG) See page 86. A/D Conversion Value Data $001D Register (ADC) See page 96. Figure 2-3. I/O and Control Registers (Sheet MC68HC05P18A MOTOROLA Bit Read: ICRL7 ICRL6 ICRL5 Write: Reset: Read: OCRH7 OCRH6 OCRH5 Write: ...
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... Unimplemented R 8000 bytes at locations $1FC0–$3EFF 48 bytes in page zero locations $0020–$004F 16 additional bytes for user vectors at locations $3FF0–$3FFF Memory Map Bit 0 0 CH2 CH1 CH0 Reserved U = Unaffected MC68HC05P18A MOTOROLA ...
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... Technical Data — MC68HC05P18A 3.1 Contents 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 3.2 Introduction This section describes the central processor unit (CPU) registers. MC68HC05P18A MOTOROLA Section 3. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Arithmetic/Logic Unit .38 Central Processor Unit (CPU) Technical Data 33 ...
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... PCL HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG Figure 3-1. Programming Model Central Processor Unit (CPU) ACCUMULATOR (A) 0 INDEX REGISTER (X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) MC68HC05P18A MOTOROLA ...
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... During a reset or after the reset stack pointer (RSP) instruction, the stack pointer is preset to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. MC68HC05P18A MOTOROLA Bit Unaffected by reset Figure 3-2 ...
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... Figure 3-5. Program Counter (PC) Technical Data Figure 3-4. Stack Pointer (SP Loaded with vectors from $3FF3 and $3FFF Central Processor Unit (CPU) Bit Bit MC68HC05P18A MOTOROLA ...
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... After any reset, the interrupt mask is set and can be cleared only by a software instruction. Negative Flag The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. MC68HC05P18A MOTOROLA Bit ...
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... Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations. Technical Data 38 Central Processor Unit (CPU) MC68HC05P18A MOTOROLA ...
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... Non-maskable software interrupt instruction (SWI) 2. External asynchronous interrupt (IRQ) 3. Input capture interrupt (TIMER) 4. Output compare interrupt (TIMER) 5. Timer overflow interrupt (TIMER) 6. Port A interrupt, if selected as a mask option MC68HC05P18A MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .42 Software Interrupt (SWI .42 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 External Interrupt (IRQ) ...
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... Vector Address Interrupt RESET $3FFE–$3FFF SWI $3FFC–$3FFD IRQ $3FFA–$3FFB TIMER $3FF8–$3FF9 TIMER $3FF8–$3FF9 TIMER $3FF8–$3FF9 N/A $3FF6–$3FF7 N/A $3FF4–$3FF5 N/A $3FF2–$3FF3 N/A $3FF0–$3FF1 MC68HC05P18A MOTOROLA ...
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... CPU state to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. that occur during interrupt processing. MC68HC05P18A MOTOROLA Figure 4-1 FROM RESET IS I BIT Y SET? N IRQ Y INTERRUPT? N TIMER ...
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... Hardware interrupts The program to vector to its starting address, which is specified by the contents of memory locations $3FFE and $3FFF The I bit in the condition code register (CCR set The MCU to be configured to a known state as described in Section 5. Resets. Interrupts Figure 4-1. A low-level input MC68HC05P18A MOTOROLA ...
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... Input Capture Interrupt The input capture interrupt is generated by the 16-bit timer as described in Section 8. 16-Bit MC68HC05P18A MOTOROLA External interrupt (IRQ) Input capture interrupt Output compare interrupt Timer overflow interrupt Timer. The input capture interrupt flag is located in Interrupts ...
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... This internal interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $3FF8 and $3FF9. Technical Data 44 Section 8. 16-Bit Timer. The output compare interrupt flag Timer. The timer overflow interrupt flag is located in Interrupts MC68HC05P18A MOTOROLA ...
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... The RESET pin is an input with a Schmitt trigger as shown in Figure reset signal (RST), which is the logical OR of internal reset functions and is clocked by PH2. MC68HC05P18A MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 External Reset (RESET .46 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Power-On Reset (POR .47 Computer Operating Properly (COP) Reset . . . . . . . . . . . . .47 Low-Voltage Reset (LVR .48 ...
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... The three internally generated resets are: • • • Technical Data 46 CLOCKED ONE-SHOT PH2 PH2 Figure 5-1. Reset Block Diagram Section 13. Electrical Initial power-on reset (POR) Computer operating properly (COP) watchdog timer Low-voltage reset (LVR) Resets TO IRQ LOGIC CPU OTHER LATCH PERIPHERALS RST Specifications. MC68HC05P18A MOTOROLA ...
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... The COP register is shared with the most-significant bit (MSB unimplemented user interrupt vector, as shown in this location returns the MSB of the unimplemented user interrupt vector. Writing to this location clears the COP watchdog timer. Address: Read: Write: Reset: MC68HC05P18A MOTOROLA $3FF0 Bit ...
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... The LVR generates the RST signal, which resets the CPU and other peripherals. If any other reset function is active at the end of the LVR reset signal, the RST signal remains in the reset condition until the other reset condition(s) end. Technical Data 48 supply voltage is below reasonable DD Resets DD MC68HC05P18A MOTOROLA ...
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... Introduction The MC68HC05P18A has one user mode of operation and several low- power modes which are described in this section. MC68HC05P18A MOTOROLA Section 6. Operating Modes Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Halt Mode .53 WAIT Instruction .53 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .54 Operating Modes ...
Page 50
... The flow of the stop, halt, and wait modes is shown in Figure Technical Data 50 An 8-bit input/output (I/O) port A second 8-bit I/O port shared with the analog-to-digital (A/D) subsystem One 3-bit I/O port shared with the serial input/output port (SIOP) One 2-bit I/O port shared with the 16-bit timer subsystem 6-1. Operating Modes MC68HC05P18A MOTOROLA ...
Page 51
... N IRQ Y EXTERNAL INTERRUPT? RESTART EXTERNAL N OSCILLATOR START STABILIZATION DELAY OF STABILIZATION Figure 6-1. Stop, Halt, and Wait Modes Flowchart MC68HC05P18A MOTOROLA HALT EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE STOP RC OSCILLATOR STOP INTERNAL PROCESSOR CLOCK CLEAR I BIT IN CCR LVR Y OR EXTERNAL RESET? ...
Page 52
... M68HC05 Family and places the MCU in stop mode. instruction behaves like a WAIT instruction (with the exception of a brief delay at startup) and places the MCU in halt mode. An IRQ external interrupt Port A external interrupt, if selected as a mask option An externally generated reset Operating Modes MC68HC05P18A MOTOROLA ...
Page 53
... COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the condition code register, enabling the IRQ external interrupt. All other registers, memory, and input/output lines remain in their previous state. MC68HC05P18A MOTOROLA Operating Modes Operating Modes Low-Power Modes Technical Data ...
Page 54
... WAIT time less than COP timeout WAIT time MORE than COP timeout Any length WAIT time Operating Modes Table 6-1. THEN the COP Watchdog Timer Should: Enable or disable COP via mask option Disable COP via mask option Disable COP via mask option MC68HC05P18A MOTOROLA ...
Page 55
... These ports are programmable as either inputs or outputs under software control of the data direction registers (DDRs). There is also an input-only pin associated with port D. MC68HC05P18A MOTOROLA Section 7. Input/Output (I/O) Ports Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port .56 Port .57 Port .58 Port .59 I/O Port Programming .60 ...
Page 56
... READ $0000 INTERNAL HC05 DATA BUS RESET (RST) Technical Data 56 Figure DATA DIRECTION REGISTER BIT DATA REGISTER BIT MASK OPTION (PULLUP INHIBIT) Figure 7-1. Port A I/O Circuitry Input/Output (I/O) Ports 7-1. Each port A pin is controlled I/O OUTPUT PIN 100 A PULLUP IRQ INTERRUPT SYSTEM MC68HC05P18A MOTOROLA ...
Page 57
... See (SIOP) READ $0005 WRITE $0005 RESET (RST) WRITE $0001 READ $0001 INTERNAL HC05 DATA BUS MC68HC05P18A MOTOROLA Figure 7-2). Section 9. Serial Input/Output Ports for a discussion of the SIOP subsystem. DATA DIRECTION REGISTER BIT DATA REGISTER BIT Figure 7-2. Port B I/O Circuitry Input/Output (I/O) Ports ...
Page 58
... Technical Data 58 7-3). Two port C pins, PC0 and PC1, can source and sink a regarding current specifications. DATA DIRECTION REGISTER BIT DATA REGISTER BIT Figure 7-3. Port C I/O Circuitry Input/Output (I/O) Ports Section 13. Electrical Converter. HIGH CURRENT CAPABILITY, PC0 AND PC1 ONLY I/O OUTPUT PIN MC68HC05P18A MOTOROLA ...
Page 59
... D data register at any time. READ $0007 WRITE $0007 RESET (RST) WRITE $0003 READ $0003 INTERNAL HC05 DATA BUS MC68HC05P18A MOTOROLA One bidirectional pin, PD5/CKOUT One input-only pin, PD7 DATA DIRECTION REGISTER BIT DATA REGISTER BIT Figure 7-4. Port D I/O Circuitry Input/Output (I/O) Ports Input/Output (I/O) Ports ...
Page 60
... Access to Data Register @ $0000 Read Write I/O pin See note PA0–PA7 PA0–PA7 Access to Data Register @ $0001 Read Write I/O pin See note PB5–PB7 PB5–PB7 Access to Data Register @ $0002 Read Write I/O pin See note PC0–PC7 PC0–PC7 MC68HC05P18A MOTOROLA ...
Page 61
... Note: Does not affect input, but stored to data register NOTE: To avoid generating a glitch on an I/O port pin, data should be written to the I/O port data register before writing a logical 1 to the corresponding data direction register. MC68HC05P18A MOTOROLA Table 7-4. Port D I/O Pin Functions to DDRD @ $0007 I/O Pin Mode Read/Write 0 ...
Page 62
... Input/Output (I/O) Ports Technical Data 62 Input/Output (I/O) Ports MC68HC05P18A MOTOROLA ...
Page 63
... Pulse widths can vary from microseconds to seconds depending on the oscillator frequency selected. The 16-bit timer is also capable of generating periodic interrupts. See MC68HC05P18A MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Timer .65 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Timer Status Register ...
Page 64
... INTERNAL HC05 BUS PH2 BUFFER CLOCK FREE- RUNNING COUNTER TMRH/ACRH TMRL/ACRL OVERFLOW DETECTOR TOF ICF INTERRUPT GENERATOR OCIE TOIE ICIE 16-Bit Timer INPUT CAPTURE ICRH ICRL 4 EDGE TCAP DETECTOR TCMP D Q > R RESET TIMER INTERRUPT TIMER CONTROL IEDG OLVL REGISTER MC68HC05P18A MOTOROLA ...
Page 65
... When reading either the timer or alternate counter registers, if the MSB is read, the LSB must also be read to complete the read sequence. See MC68HC05P18A MOTOROLA The timer registers, TMRH and TMRL The alternate counter registers, ACRH and ACRL Figure 8-2 and Figure 8-3 ...
Page 66
... ACRL5 ACRL4 Unimplemented 16-Bit Timer Bit 0 TMRH3 TMRH2 TMRH1 TMRH0 Bit 0 TMRL3 TMRL2 TMRL1 TMRL0 Bit 0 ACRH3 ACRH2 ACRH1 ACRH0 Bit 0 ACRL3 ACRL2 ACRL1 ACRL0 MC68HC05P18A MOTOROLA ...
Page 67
... PH2 CLOCK INTERNAL RESET 16-BIT FREE-RUNNING COUNTER RESET (EXTERNAL OR OTHER) Note: The counter and control registers are the only 16-bit timer registers affected by reset. Figure 8-5. State Timing Diagram for Timer Reset MC68HC05P18A MOTOROLA 8-4. $FFFF $0000 $FFFC $FFFD 16-Bit Timer 16-Bit Timer Timer Figure 8-5 ...
Page 68
... Bit OCRH7 OCRH6 OCRH5 OCRH4 Unaffected by reset $0017 Bit OCRL7 OCRL6 OCRL5 OCRL4 Unaffected by reset Figure 8-6. Output Compare Registers (OCRH/OCRL) 16-Bit Timer Figure 8- Bit 0 OCRH3 OCRH2 OCRH1 OCRH0 Bit 0 OCRL3 OCRL2 OCRL1 OCRL0 MC68HC05P18A MOTOROLA ...
Page 69
... This procedure prevents the output compare flag bit (OCF) from being set between the time it is read and the time the output compare registers are updated. A software example is shown in MC68HC05P18A MOTOROLA (CCR). inhibit further compares until the LSB is written. flag (OCF). ...
Page 70
... ICRH5 ICRH4 Unaffected by reset $0015 Bit ICRL7 ICRL6 ICRL5 ICRL4 Unaffected by reset Figure 8-8. Input Capture Registers (ICRH/ICRL) Figure 8-9). This delay is required for internal 16-Bit Timer Bit 0 ICRH3 ICRH2 ICRH1 ICRH0 Bit 0 ICRL3 ICRL2 ICRL1 ICRL0 MC68HC05P18A MOTOROLA ...
Page 71
... Note: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture flag is set during the next T11 timer state. Figure 8-9. State Timing Diagram for Input Capture MC68HC05P18A MOTOROLA $FFEC $FFED 16-Bit Timer ...
Page 72
... Clearing this bit will select the falling edge, setting it selects the rising edge. Technical Data 72 Figure 8-10 $0012 Bit ICIE OCIE TOIE Unimplemented Figure 8-10. Timer Control Register (TCR) 16-Bit Timer and free-running counter Bit IEDG OLVL Unaffected MC68HC05P18A MOTOROLA ...
Page 73
... The alternate counter registers (ACRH and ACRL) contain the same values as the timer registers (TMRH and TMRL). Registers ACRH and ACRL can be read at any time without affecting the timer overflow flag (TOF) or interrupt. Address: Read: Write: Reset: MC68HC05P18A MOTOROLA purpose of servicing the flag or interrupt. $0013 Bit ICF OCF TOF ...
Page 74
... If a valid input capture edge occurs at the TCAP pin during stop mode, the input capture detect circuitry is armed. This action does not set any flags or wake up the MCU, but when the MCU does wake up there will Technical Data 74 16-Bit Timer MC68HC05P18A MOTOROLA ...
Page 75
... If the stop mode is exited by an external RESET, no input capture flag or data will be present even if a valid input capture edge was detected during stop mode. MC68HC05P18A MOTOROLA Timer Operating during Stop Mode 16-Bit Timer 16-Bit Timer Technical Data ...
Page 76
... Timer Technical Data 76 16-Bit Timer MC68HC05P18A MOTOROLA ...
Page 77
... SIOP is enabled, SPE bit set in the SIOP control register (SCR), port B data direction register (DDR), and data register are modified by the SIOP. Although port B DDR and data registers can be altered by MC68HC05P18A MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Serial Clock (SCK .78 Serial Data Input (SDI .79 Serial Data Output (SDO) ...
Page 78
... HCO5 INTERNAL BUS SPE 8-BIT SDO STATUS SHIFT REGISTER SDI REGISTER $0C $0B SCK Figure 9-1. SIOP Block Diagram Figure 9-2). Data is captured at the SDI pin on the Serial Input/Output Ports (SIOP) SDO/PB5 I/O CONTROL LOGIC SDI/PB6 SCK/PB7 MC68HC05P18A MOTOROLA ...
Page 79
... Prior to enabling the SIOP, PB5 can be initialized to determine the beginning state. While the SIOP is enabled, PB5 cannot be used as a standard output since that pin is connected to the last stage of the SIOP serial shift register. A mask option is included to allow the data to MC68HC05P18A MOTOROLA BIT 1 BIT 2 BIT 3 BIT 4 ...
Page 80
... SIOP data register (SDR) located at address $000C shows the position of each bit in the register and indicates $000A Bit SPE MSTR Unimplemented Figure 9-3. SIOP Control Register (SCR) Serial Input/Output Ports (SIOP) Figure 9- Bit MC68HC05P18A MOTOROLA ...
Page 81
... SPE bit. Clearing the MSTR bit will abort any transfers that may have been in progress. Reset clears the MSTR bit, placing the SIOP subsystem in slave mode. MC68HC05P18A MOTOROLA 1. Abort the transmission 2. Reset the serial bit counter 3. Convert the port B/SIOP port to a general-purpose I/O port ...
Page 82
... Reset clears the DCOL bit. Technical Data 82 shows the position of each bit in the register and indicates $000B Bit SPIF DCOL Unimplemented Figure 9-4. SIOP Status Register (SSR) Serial Input/Output Ports (SIOP Bit MC68HC05P18A MOTOROLA ...
Page 83
... DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause invalid data to be transmitted and/or received. Figure 9-5 not affected by reset. Address: Read: Write: Reset: MC68HC05P18A MOTOROLA shows the position of each bit in the register. This register is $000C Bit SD7 SD6 ...
Page 84
... Serial Input/Output Ports (SIOP) Technical Data 84 Serial Input/Output Ports (SIOP) MC68HC05P18A MOTOROLA ...
Page 85
... The electrically erasable programmable read-only memory (EEPROM) is located at address $0140 and consists of 128 bytes. Programming the EEPROM can be done by the user on a single byte basis by manipulating the programming register, located at address $001C. MC68HC05P18A MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . .86 Programming/Erasing Procedures . . . . . . . . . . . . . . . . . . . . . .88 EEPROM Section 10 ...
Page 86
... CPEN ER1 Unimplemented Table 10-1 Table 10-1. Erase Mode Select ER1 ER0 EEPROM Bit 0 ER0 LATCH EERC EEPGM shows the modes Mode Program, no erase Byte erase Block erase Bulk erase MC68HC05P18A MOTOROLA ...
Page 87
... LATCH = 1. If LATCH is not set, EEPGM cannot be set. LATCH and EEPGM cannot both be set with one write if LATCH is cleared. EEPGM is cleared automatically when LATCH is cleared. Reset clears this bit. MC68HC05P18A MOTOROLA EEPROM Programming Register , to allow the RC oscillator to stabilize. RCON EEPROM ...
Page 88
... Set LATCH = 1, CPEN = 1, ER1 = 1, and ER0 = 0. 2. Write to any address in the block. 3. Set EEPGM for a time, t Technical Data 88 EEPGM If PB • — Program the new data over the existing data without erasing it first • — Erase byte before programming. . EBYT EBLOCK EEPROM . . MC68HC05P18A MOTOROLA ...
Page 89
... Set EEPGM for a time terminate the programming or erase sequence, clear EEPGM, delay for a time, t LATCH and CPEN to free up the buses. Following each erase or programming sequence, clear all programming control bits. MC68HC05P18A MOTOROLA . EBULK , to allow the programming voltage to fall, and then clear FPV EEPROM ...
Page 90
... EEPROM Technical Data 90 EEPROM MC68HC05P18A MOTOROLA ...
Page 91
... Introduction The MC68HC05P18A includes a 4-channel, multiplexed input, 8-bit, successive approximation analog-to-digital (A/D) converter. The A/D subsystem shares its inputs with port C pins PC3–PC7. MC68HC05P18A MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Reference Supply Voltage (V Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Digital Section .93 Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Internal versus External Oscillator ...
Page 92
... For ratiometric should be at the same potential as the supply REFH . SS ) REFH pin internally and V ; however, the accuracy of conversions REFH Analog-to-Digital (A/D) Converter supplying the high REFH produces a REFH can be any REFH = 1/2 LSB (least MC68HC05P18A MOTOROLA ...
Page 93
... Electrical noise slightly degrades the accuracy of the A the PH2 clock is 1 MHz or greater (for example, external MC68HC05P18A MOTOROLA respect to the PH2 clock, the conversion complete (CC) bit in the A/D status and control register (ADSC) must be used to determine when a conversion sequence has been completed. ...
Page 94
... CC bit. Technical Data 94 Oscillator selection Analog subsystem power Input channel selection 11-1. $001E Bit ADON Unimplemented R Analog-to-Digital (A/D) Converter Bit 0 0 CH2 CH1 CH0 Reserved MC68HC05P18A MOTOROLA ...
Page 95
... C pin reads as a logic 0. The remaining port C pins read normally. To digitally read a port C pin, the A/D subsystem must be disabled (ADON = 0) or input channel 5–7 must be selected. MC68HC05P18A MOTOROLA to stabilize before accurate conversion results can be attained. ADON Table 11-1. A/D Multiplexer Input Channel Assignments ...
Page 96
... MC68HC05P18A when coming out of stop mode are sufficient for this purpose. No explicit delays need to be added to the application software. Technical Data 96 $001D Bit AD7 AD6 AD5 AD4 Unaffected by reset = Unimplemented R Analog-to-Digital (A/D) Converter Figure 11- Bit 0 AD3 AD2 AD1 AD0 = Reserved MC68HC05P18A MOTOROLA ...
Page 97
... MC68HC05P18A MOTOROLA Section 12. Instruction Set Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Immediate .99 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Indexed, 8-Bit Offset .100 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Register/Memory Instructions .102 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .103 Jump/Branch Instructions .104 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .106 Control Instructions ...
Page 98
... The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: • • • • • • • • Technical Data 98 Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative Instruction Set MC68HC05P18A MOTOROLA ...
Page 99
... The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. ...
Page 100
... The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. Technical Data 100 ...
Page 101
... When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. ...
Page 102
... OR accumulator with memory byte Subtract memory byte and carry bit from accumulator Store accumulator in memory Store index register in memory Subtract memory byte from accumulator Instruction Set Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB MC68HC05P18A MOTOROLA ...
Page 103
... These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. MC68HC05P18A MOTOROLA Table 12-2. Read-Modify-Write Instructions Instruction Arithmetic shift left (same as LSL) Arithmetic shift right Bit clear ...
Page 104
... The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Technical Data 104 Instruction Set MC68HC05P18A MOTOROLA ...
Page 105
... MC68HC05P18A MOTOROLA Table 12-3. Jump and Branch Instructions Instruction Branch if carry bit clear Branch if carry bit set Branch if equal Branch if half-carry bit clear Branch if half-carry bit set Branch if higher Branch if higher or same Branch if IRQ pin high Branch if IRQ pin low Branch if lower ...
Page 106
... CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Technical Data 106 Table 12-4. Bit Manipulation Instructions Instruction Bit clear Branch if bit clear Branch if bit set Bit set Instruction Set Mnemonic BCLR BRCLR BRSET BSET MC68HC05P18A MOTOROLA ...
Page 107
... Control Instructions These instructions act on CPU registers and control CPU operation during program execution. MC68HC05P18A MOTOROLA Table 12-5. Control Instructions Instruction Clear carry bit Clear interrupt mask No operation Reset stack pointer Return from interrupt Return from subroutine Set carry bit Set interrupt mask ...
Page 108
... REL DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 REL REL REL REL REL REL MC68HC05P18A MOTOROLA ...
Page 109
... Branch Never BRSET n opr rel Branch if Bit n Set BSET n opr Set Bit n BSR rel Branch to Subroutine CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC05P18A MOTOROLA Description PC (PC rel ? IRQ = 1 PC (PC rel ? IRQ = 0 (A) (M) PC (PC rel ? (PC rel ? — ...
Page 110
... IMM DIR EXT C8 4 — IX2 IX1 DIR 3C 5 INH 4C 3 — INH 5C 3 IX1 DIR EXT IX2 IX1 MC68HC05P18A MOTOROLA ...
Page 111
... Logical OR Accumulator with Memory ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX Rotate Byte Left through Carry Bit ROL opr,X ROL ,X MC68HC05P18A MOTOROLA Description PC (PC Push (PCL); SP (SP) – 1 Push (PCH); SP (SP) – Effective Address A (M) ...
Page 112
... IX2 IX1 INH DIR EXT — IX2 IX1 IMM DIR EXT IX2 IX1 INH 83 0 INH 97 2 MC68HC05P18A MOTOROLA ...
Page 113
... Indexed, no offset addressing mode IX1 Indexed, 8-bit offset addressing mode IX2 Indexed, 16-bit offset addressing mode M Memory location N Negative flag n Any bit MC68HC05P18A MOTOROLA Description (M) – $00 A (X) opr Operand (one or two bytes) PC Program counter PCH Program counter high byte PCL Program counter low byte ...
Page 114
Bit Manipulation Branch DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 ...
Page 115
... PD5 Clock Out Timing (PD5 Clock Out Option Enabled .122 13.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 MC68HC05P18A MOTOROLA Section 13. Electrical Specifications Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Operating Temperature Range .116 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Power Considerations .117 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .118 Active Reset Characteristics .119 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .120 SIOP Timing ...
Page 116
... Electrical Specifications within the range Out Value Unit V –0 –0 +0 –65 to +150 STG for guaranteed Symbol Value Unit + –40 to +85 –40 to +125 T 150 J Symbol Value Unit 60 C MC68HC05P18A MOTOROLA ...
Page 117
... Where: For most applications, P Ignoring P Solving equations (1) and (2) for K gives: where constant pertaining to the particular part. K can be determined from equation (3) by measuring P known T by solving equations (1) and (2) iteratively for any value of T MC68HC05P18A MOTOROLA ambient temperature ...
Page 118
... Unit — 0 –0.1 — –0.8 — — 0 — — 3.5 mA — 2.5 mA — — 4.5 mA — 4.6 mA — — 200 A — — — — — 8 Continued MC68HC05P18A MOTOROLA ...
Page 119
... PD5 enabled and disabled and LVR enabled and disabled. DD 13.7 Active Reset Characteristics Rise Time Fall Time 0.5 s 1.0 s 2.5 s Note 4.5 Vdc Vdc MC68HC05P18A MOTOROLA (1) = – +125 C, unless otherwise noted. All values shown reflect average OSC2 L = 0.2 Vdc Pulse Width ...
Page 120
... Inherent (within total error Hex Hex (Note 3) — REFH = 0 Vdc +125 C, unless otherwise noted A Electrical Specifications Comments Including quantization A/D accuracy may decrease proportionately REFH reduced below 4 REFH MC68HC05P18A MOTOROLA ...
Page 121
... SDI hold time 5.0 Vdc 10 Vdc OSC CYC OP MC68HC05P18A MOTOROLA t 1 BIT 0 BIT 1 ... BIT 0 BIT 1 ... 6 Figure 13-1. SIOP Timing Diagram (1) Characteristic +125 C, unless otherwise noted A Electrical Specifications Electrical Specifications SIOP Timing ...
Page 122
... Minimum rise and fall times assume 55% duty cycle. Technical Data 122 (1) (2) (4) Figure 13-2. PD5 Clock Out Timing Characteristic Symbol Electrical Specifications (3) (5) Min Max Unit t ns CYC 3 7.5 27 — Maximum rise and DD MC68HC05P18A MOTOROLA ...
Page 123
... Vdc The minimum period should not be less than the number of cycles it takes to execute the interrupt service routine ILIL plus CYC MC68HC05P18A MOTOROLA (1) = – +125 C, unless otherwise noted Electrical Specifications Electrical Specifications Control Timing Symbol Min Max f — ...
Page 124
VDDR V DD THRESHOLD (1-2 V TYPICAL (2) OSC1 4064 t CYC t CYC INTERNAL PROCESSOR (1) CLOCK INTERNAL ADDRESS 3FFE 3FFF (1) ...
Page 125
... MC68HC05P18A MOTOROLA Section 14. Mechanical Specifications Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 28-Pin Plastic Dual In-Line Package (Case #710 .126 28-Pin Small Outline Package (Case #751F .126 Local Motorola Sales Office Motorola Mfax – Phone 602-244-6609 – EMAIL rmfax0@email.sps.mot.com Worldwide Web (wwweb) at http://design-net.com Mechanical Specifications ...
Page 126
... TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 17.80 18.05 0.701 0.711 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.41 0.90 0.016 0.035 F 1.27 BSC 0.050 BSC G J 0.23 0.32 0.009 0.013 K 0.13 0.29 0.005 0.011 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 MC68HC05P18A MOTOROLA ...
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... MC68HC05P18AP (standard) MC68HC05P18ADW (standard) MC68HC05P18ACP (extended) MC68HC05P18ACDW (extended) MC68HC05P18AMP (automotive) MC68HC05P18AMDW (automotive Plastic dual in-line package MC68HC05P18A MOTOROLA Section 15. Ordering Information Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 shows the MC order numbers for the available package Table 15-1. MC Order Numbers (1) MC Order Number ...
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... Ordering Information Technical Data 128 Ordering Information MC68HC05P18A MOTOROLA ...
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